Si5367

2

Preliminary Rev. 0.3

Table 1. Performance Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Temperature Range

–40

25

85

ºC

Supply Voltage

2.25

2.5

2.75

V

1.62

1.8

1.98

V

Supply Current

All CKOUTs enabled

LVPECL format output

—394

435

mA

Only CKOUT1 enabled

—

253

284

mA

All CKOUTs enabled

CMOS format output

—278

321

mA

Only CKOUT1 enabled

—

229

261

mA

Tristate/Sleep Mode

—

TBD

TBD

mA

Input Clock Frequency

(CKIN1, CKIN2, CKIN3,

CKIN4)

Input frequency and clock

multiplication ratio determined

by programming device PLL

dividers. Consult Silicon Labo-

ratories configuration software

DSPLLsim or Any-Rate Preci-

sion Clock Family Reference

Manual at www.silabs.com/tim-

ing to determine PLL divider

settings for a given input fre-

quency/clock multiplication

ratio combination.

10

—

707.35

MHz

Output Clock Frequency

(CKOUT1, CKOUT2,

CKOUT3, CKOUT4,

CKOUT5)

10

970

1213

—

—

—

945

1134

1417

MHz

Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)

0.25

—

1.9

Common Mode Voltage

1.8 V ±10%

0.9

—

1.4

V

2.5 V ±10%

1.0

—

1.7

V

Rise/Fall Time

20–80%

—

—

11

ns

Duty Cycle

Whichever is less

40

—

60

%

50

—

ns

Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5)

Common Mode

LVPECL

100

Ω load

line-to-line

1.42

1.25

V

Differential Output Swing

1.1

—

1.9

V

Single Ended Output

Swing

0.5

—

0.93

V

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision

Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.