8.2.1.2.2 Meeting the Watchdog Timeout Period

The watchdog timeout design requirement can be met either by using a fixed-timeout version of the TPS35-

Q1 or by connecting a capacitor between the CWD pin and GND. The typical values can be met with

preprogrammed fixed time options, hence a pinout offering fixed time options is selected. Please see the Timing

Requirements for a list of fixed timeouts. If using the CWD feature, pinout A or B must be used; please refer

to tWD Timer for instructions on how to program the timout period. The design requirement in this example is

tWD = 1.6s. This is one of the fixed timeout options offered by pinout C or D. Thus the possible variant option is

narrowed down to TPS35Cx13KAxDDFRQ1.

8.2.1.2.3 Setting the Reset Delay

The reset delay requirement can be met either by using a fixed-timeout version of the TPS35-Q1 or by

connecting a capacitor between the CRST pin and GND. The typical values can be met with preprogrammed

fixed time options, hence a pinout offering fixed time options is selected. Please see the Timing Requirements

for a list of fixed timeouts. If using the CRST feature, pinout A or B must be used; please refer to the Timing

Specifications for instructions on how to program the timout period. The design requirement in this example is tD

= 200ms. Thus the possible variant option is narrowed down to TPS35Cx13KAGDDFRQ1.

8.2.1.2.4 Setting the Startup Delay and Output Topology

The startup delay and output topology are set by the device variant. Please refer to Device Comparison for the

possible options. A minimum startup delay of 700ms and open-drain output are desired, thus Option D, 1s typical

startup delay and open-drain active-low, is selected. Thus the option suitable to meet design requirements is

TPS35CD13KAGDDFRQ1.

8.2.1.2.5 Calculating the RESET Pullup Resistor

The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in Figure 8-2. When the

FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls

the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen

to make sure that VOL is below the maximum value. To choose the proper pullup resistor, there are three key

specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST),

and VOL. The maximum VOL is 0.3V, meaning that the effective resistor divider created must be able to bring the

voltage on the reset pin below 0.3V with IRST kept below 2mA for VDD ≥ 3V and 500μA for VDD = 1.5V. For this

example, with a VPU =VDD = 1.5V, a resistor must be chosen to keep IRST below 500μA because this value is the

maximum consumption current allowed. To make sure this specification is met, a pullup resistor value of 10kΩ

was selected, which sinks a maximum of 180μA when RESET is asserted.

RESET

VDD

RESET

CONTROL

Figure 8-2. Open-Drain RESET Configuration

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TPS35-Q1

SLVSGE8B – NOVEMBER 2022 – REVISED AUGUST 2024

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Product Folder Links: TPS35-Q1