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YSS952 Datasheet(PDF) 37 Page - YAMAHA CORPORATION |
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YSS952 Datasheet(HTML) 37 Page - YAMAHA CORPORATION |
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37 / 116 page  3 FUNCTION DESCRIPTION YSS952 6SS952A30 37 PIO = 0x1 AIFMD[3:0] 0x0 0x1 0x2 0x3 Mode Name 2ch SDI + 4ch SDI 2ch SDI on SDI0 2ch SDI on SDI1 2ch SDI on SDI2 Signal Name Direction Signal Name Direction Signal Name Direction Signal Name Direction GPIO0 WCK Input Input WCK Input 0 Input WCK Input 0 Input WCK Input 0 Input GPIO1 BCK Input Input BCK Input 0 Input BCK Input 0 Input BCK Input 0 Input GPIO2 SDI0 Input SDI0 Input SDI0 Input SDI0 Input GPIO3 GPIO3 IO WCK Input1 Input WCK Input 1 Input WCK Input1 Input GPIO4 GPIO4 IO BCK Input1 Input BCK Input 1 Input BCK Input1 Input GPIO5 GPIO5 IO SDI1 Input SDI1 Input SDI1 Input GPIO6 GPIO6 IO WCK Input2 Input WCK Input2 Input WCK Input 2 Input GPIO7 GPIO7 IO BCK Input2 Input BCK Input2 Input BCK Input 2 Input GPIO8 GPIO8 IO SDI2 Input SDI2 Input SDI2 Input GPIO9 GPIO9 IO GPIO9 IO GPIO9 IO GPIO9 IO GPIO10 GPIO10 IO GPIO10 IO GPIO10 IO GPIO10 IO GPIO11 GPIO11 IO GPIO11 IO GPIO11 IO GPIO11 IO [Note 1] [Note 2] [Note 3] [Note 1] GPIO2-0 (SDI0) inputs will be routed to SRC. [Note 2] GPIO5-3 (SDI1) inputs will be routed to SRC. [Note 3] GPIO8-6 (SDI2) inputs will be routed to SRC. Indicates the following data and clocks. • An external clock and audio signal samples synchronized to the external clock. • Audio clock derived from an external audio clock and audio signal samples synchronized to the derived clock. Audio clock derived from XIN clock and audio signal samples synchronized to the derived clock. GPIO pins. Unused pins, disconnected from the internal circuits. ・ GPIO11–0 inputs will be ignored when PI is logic 0. They can tolerate floating voltage levels and it will not propagate inside the device. ・ On initialization of the device, set PI to logic 1 when configuring AIFMD [3:0] and PIO registers. For the configuration detail of these registers, see "3.7.7.1 Powering Up, Initialization" ・ When configuring a GPIO pin for output, set the corresponding bit in POEN register first before setting PI to logic 1. For the detail of GPIO port configuration, see "3.3.8.1 GPIO Port Data Direction Registers". |
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