Feature Description

Watchdog Input

The TPV710 features a watchdog timer, which monitors microprocessor activity. A timer circuit is cleared with every low-to-

high or high-to-low logic transition on the watchdog input pin (WDI). If the timer counts through the watchdog timeout period

(tWD), WDO is asserted. The microprocessor is required to toggle the WDI pin to avoid being reset.

Enable Control

TPV710 has EN pin to control the watchdog timer, if EN is pull low, the watchdog timer is enabled, if EN is pull high, the

watchdog timer is disabled and the timer count is cleared. EN has internal pull down resistor, which means watchdog timer is

enabled if EN is not connected. In addition to EN control, the watchdog timer is also cleared by an under-voltage condition on

VCC. After VCC ramps above VUV, the watchdog timer can be controlled by EN control, and the timer starts counting.

Watchdog Output

When watchdog timer out occurs, the WDO goes low for tPR, and then goes high. If no WDI toggling, WDO goes low again

after tWD.

VCC

VSTART

WDI

WDO

<tWD

(0 or 1, not float)

EN

tWD

tRP

tWD

tRP

Figure 4. Watchdog Timing Diagram

TPV710

Watchdog Timer Circuit with EN Control

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GA20230701A1