59C11

DS20040J-page 4

© 1996 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

START Condition

The START bit is detected by the device if CS and DI

are both High with respect to the positive edge of CLK

for the first time.

Before a START condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition) without resulting in any device oper-

ation (READ, WRITE, EWEN, EWDS, ERAL, and

WRAL). As soon as CS is HIGH, the device is no longer

in the standby mode.

An instruction following a START condition will only be

executed if the required amount of opcode, address

and data bits for any particular instruction is clocked in.

After execution of an instruction (i.e. clock in or out of

the last required address or data bit) CLK and DI

become don't care bits until a new start condition is

detected.

2.2

DI/DO Pins

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero” that

precedes the READ operation, if A0 is a logic high level.

Under such a condition the voltage level seen at Data

Out is undefined and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0, the

higher the voltage at the Data Out pin.

2.3

Data Protection

During power-up, all modes of operation are inhibited

down, the source data protection circuitry acts to inhibit

The EWEN and EWDS commands give additional pro-

tection against accidentally programming during nor-

mal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, EWEN instruction must be

performed before any WRITE, ERAL or WRAL instruc-

tion can be executed. After programming is completed,

the EWDS instruction offers added protection against

unintended data changes.

Note:

CS must go LOW between consecutive

instructions.

2.4

READ Mode

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

bit (logical 0) precedes the 8- or 16-bit output string.

The output data changes during the high state of the

the positive edge of CLK, which was used to clock in the

last address bit (A0). Therefore, care must be taken if

DI and DO are connected together as a bus contention

will occur for one clock cycle if A0 is a one.

DO will go into HIGH-Z mode with the positive edge of

the next CLK cycle. This follows the output of the last

data bit D0 or the negative edge of CS, whichever

occurs first. D0 remains stable between CLK cycles for

an unlimited time as long as CS stays HIGH.

The most significant data bit (D15 or D7) is always out-

put first, followed by the lower significant bits (D14 - D0

or D6 - D0).

2.5

WRITE

The WRITE instruction is followed by 8 or 16 bits of data

which are written into the specified address. The most

significant data bit (D15 or D7) has to be clocked in first

followed by the lower significant data bits (D14 – D0 or

D6 – D0). If a WRITE instruction is recognized by the

device and all data bits have been clocked in, the

device performs an automatic erase cycle on the spec-

ified address before the data are written. The WRITE

cycle is completely self timed and commences auto-

matically after the rising edge of the CLK signal for the

last data bit (D0).

The WRITE cycle takes 1 ms maximum for 8-bit mode

and 2 ms maximum for 16-bit mode.

2.6

Erase/Write Enable and Disable

(EWEN, EWDS)

The device is automatically in the ERASE/WRITE Dis-

able mode (EWDS) after power-up. Therefore, EWEN

instruction has to be performed before any WRITE,

ERAL, or WRAL instruction is executed by the device.

For added data protection, the device should be put in

the ERASE/WRITE Disable mode (EWDS) after pro-

gramming operations are completed.

2.7

ERASE All (ERAL)

The entire chip will be erased to logical “1s” if this

instruction is received by the device and it is in the

EWEN mode. The ERAL cycle is completely self-timed

and commences after the rising edge of the CLK signal

for the last dummy address bit. ERAL takes 15 ms max-

imum.