MSP58C20

AUDIO-BAND CONVERTER

SPSS015B – DECEMBER 1993 – REVISED JULY 1996

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

A/D

I/O

DESCRIPTION

NAME

NO.

A/D

I/O

DESCRIPTION

ADCLK

14

D

I

ADCLK is a 1.024-MHz clock input.

ADOUT

8

D

O

ADOUT is the 1-bit output of the ADC modulator and is sampled at 1.024 MHz.

AIM

5

A

I

AIM is a negative differential input for the ADC. AIP and AIM together form a balanced differential input.

The biasing of this terminal is fixed through resistors by the internal common-mode voltage source. This

terminal can be ac coupled or dc coupled. If the terminal is dc coupled, external common-mode bias

should satisfy recommended operating conditions.

AIP

4

A

I

AIP is a positive differential input for the ADC. AIP and AIM together form a balanced differential input.

The biasing of this terminal is fixed through resistors by the internal common-mode voltage source. This

terminal can be ac coupled or dc coupled. If the terminal is dc coupled, external common-mode bias

should satisfy recommended operating conditions.

AOM

17

A

O

AOM is a negative differential DAC output. AOP and AOM together form a balanced differential output.

The common-mode voltage at this terminal is fixed by the internal common-mode circuitry.

AOP

18

A

O

AOP is a positive differential DAC output. AOP and AOM together form a balanced differential output.

The common-mode voltage at this terminal is fixed by the internal common-mode circuitry.

DIGL

15

D

I

DIGL is the input level bit of the DAC and is sampled at 0.512 MHz.

DIGS

16

D

I

DIGS is the input sign bit of the DAC and is sampled at 0.512 MHz.

PWAD

6

D

I

When PWAD is high, it puts the ADC part of the circuit into a power-down mode. When both PWAD and

PWDA are high, the MSP58C20 is in a stable low-power-consumption state.

PWDA

7

D

I

When PWDA is high, it puts the DAC part of the circuit in a power-down mode. When both PWAD and

PWDA are high, the MSP58C20 is in a stable low-power-consumption state.

VSUB

1

n/a

n/a

VSUBandVSSmustbeconnectedtogethertominimizesubstratecurrentsduringpowerup,powerdown,

and normal operation.

VDD

13

n/a

n/a

VDD is the 5-V power supply.

VSS

3

n/a

n/a

VSS is ground. The internal band-gap voltage and the common-mode bias voltages are referenced to

VSS.

– 0.3 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . .

– 30 mV to 30 mV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0

°C to 70°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS unless otherwise noted.