Electronic Components Datasheet Search
  English  ▼

X  

TMS29F040 Datasheet(PDF) 11 Page - Texas Instruments

Part # TMS29F040
Description  524288 BY 8-BIT FLASH MEMORY
PDF  37 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS29F040 Datasheet(HTML) 11 Page - Texas Instruments

Back Button TMS29F040 Datasheet HTML 7Page - Texas Instruments TMS29F040 Datasheet HTML 8Page - Texas Instruments TMS29F040 Datasheet HTML 9Page - Texas Instruments TMS29F040 Datasheet HTML 10Page - Texas Instruments TMS29F040 Datasheet HTML 11Page - Texas Instruments TMS29F040 Datasheet HTML 12Page - Texas Instruments TMS29F040 Datasheet HTML 13Page - Texas Instruments TMS29F040 Datasheet HTML 14Page - Texas Instruments TMS29F040 Datasheet HTML 15Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 37 page
background image
TMS29F040
524288 BY 8-BIT
FLASH MEMORY
SMJS820C – APRIL 1996 – REVISED JUNE 1998
11
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
data protection
hardware-sector protection feature
This feature disables both programming and erase operations on any combination of one to eight sectors.
Commands to program or erase a protected sector do not change the data contained in the sector. The
data-polling and toggle bits operate for 2
µs to 100 µs and then return to valid data. This feature is enabled using
high-voltage VID (10.5 V to 12.5 V) on address pin A9 and control pin G, and VIL on control pin E. Figure 14
shows a flow chart of the sector-protect operation.
The device is delivered with all sectors unprotected. Sector-unprotect mode is available to unprotect protected
sectors. Figure 16 shows a flow chart of the sector-unprotect operation.
sector-protect operation
The sector-protect operation is activated when VCC = 5.0 V (operating at TA = 25° C), W = VIH, E = VIL, and
address pin A9 and control pin G are forced to VID. The sector-select address pins A16, A17, and A18 are used
to select the sector to be protected. Address pins A0–A8, pins A10–A15, and I/O pins DQ0 – DQ7 must be stable
and can be VIL or VIH. Once the addresses are stable, W is pulsed low for 100 µs. The operation begins on the
falling edge of W and terminates on the rising edge of W. Figure 15 shows a timing diagram of the sector-protect
operation.
sector-protect verify
Verification of sector-protection is activated when VCC = 5.0 V (operating at TA = 25° C), W = VIH, G = VIL,
E = VIL, and address pin A9 = VID. Address pins A0 and A6 are set to VIL, and A1 is set to VIH. Sector-address
pins A16, A17, and A18 select the sector to be verified. The other address pins can be VIH or VIL. If the sector
selected is protected, the DQs output 01h and if the sector selected is not protected, the DQs output 00h.
sector-unprotect operation
Prior to a sector-unprotect operation, all sectors should be protected using the sector-protect mode.
Sector-unprotect is activated when VCC = 5.0 V (operating at TA = 25° C), W = VIH, and address pin A9 and
control pins G and E are forced to VID. Address pins A6, A12, and A16 are set to VIH. The sector-select address
pins A17 and A18 can be VIL or VIH. All eight sectors are unprotected in parallel. Once the inputs are stable,
W is pulsed low for 10 ms. The unprotect operation begins on the falling edge of W and terminates on the rising
edge of W. Figure 17 shows a timing diagram of the sector-unprotect operation.
sector-unprotect verify
Verification of the sector-unprotection is activated when VCC = 5.0 V (operating at TA = 25° C), W = VIH,
G = VIL, E = VIL, and address pin A9 = VID. Select the sector to be verified. Address pins A1 and A6 are set to
VIH, and A0 is set to VIL. The other address pins can be VIH or VIL. If the sector that is selected is protected,
the DQs output 01h and if the sector selected is not protected, the DQs output 00h.
low VCC write lockout
During power up and power down, write operations are locked out for VCC less than VLKO. If VCC < VLKO, the
command input is disabled and the device is reset to the read mode. On power up, if E = VIL, W = VIL, and
G = VIH, the device does not accept commands on the rising edge of W. The device automatically powers up
in the read mode.
glitching
Pulses of less than 5 ns (typical) on G, W, or E do not issue a write cycle.
power supply considerations
Each device should have a 0.1-
µF ceramic capacitor connected between VCC and VSS to suppress circuit noise.
Printed-circuit traces to VCC should be appropriate to handle the current demand and minimize inductance.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com