PPC405EP datasheet(43/50 Pages) AMCC

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PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

AMCC

Data Sheet

Table 13. Peripheral Interface Clock Timings

Parameter

Min

Max

Units

PCIClk input frequency (asynchronous mode)

Note 1

66.66

MHz

PCIClk period (asynchronous mode)

Note 1

PCIClk input high time

40% of nominal period

60% of nominal period

PCIClk input low time

40% of nominal period

60% of nominal period

EMC0MDClk output frequency

–

2.5

MHz

EMC0MDClk period

400

–

EMC0MDClk output high time

160

–

EMC0MDClk output low time

160

–

PHY0Tx0:1Clk input frequency

2.5

MHz

PHY0Tx0:1Clk period

400

PHY0Tx0:1Clk input high time

35% of nominal period

–

PHY0Tx0:1Clk input low time

35% of nominal period

–

PHY0Rx0:1Clk input frequency

2.5

MHz

PHY0Rx0:1Clk period

400

PHY0Rx0:1Clk input high time

35% of nominal period

–

PHY0Rx0:1Clk input low time

35% of nominal period

–

PerClk output frequency

–

66.66

MHz

PerClk period

–

PerClk output high time

45% of nominal period

55% of nominal period

PerClk output low time

45% of nominal period

55% of nominal period

PerClk clock edge stability (phase jitter, cycle to cycle)

± 0.3

Note:

1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405EP Embedded Processor

User’s Manual for more information.

PPC405EP Datasheet(PDF) 43 Page - Applied Micro Circuits Corporation

PPC405EP Datasheet(HTML) 43 Page - Applied Micro Circuits Corporation

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