HT36A4 datasheet(6/38 Pages) HOLTEK

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R vs F Characteristics Curve

HT36A4

Rev. 1.10

March 12, 2007

1 2 0

1 5 0

1 8 0

2 0 0

2 2 0

2 4 0

2 7 0

3 0 0

H T 3 6 A 4 R v s . F C h a r t

1 4

1 2

1 0

R ( k W )

3 . 0 V

4 . 5 V

Function Description

Execution Flow

The system clock for the HT36A4 is derived from either

a crystal or an RC oscillator. The oscillator frequency di-

vided by 2 is the system clock for the MCU

(fOSC=fSYS

´2) and it is internally divided into four

non-overlapping clocks. One instruction cycle consists

of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to effectively execute in one cycle. If an instruction

changes the program counter, two cycles are required

to complete the instruction.

Program Counter

- PC

The 13-bit program counter (PC) controls the sequence

in which the instructions stored in program ROM are ex-

ecuted and its contents specify a maximum of 8192 ad-

dresses for each bank.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points

to the memory word containing the next instruction

code.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set, internal interrupt, external interrupt or return from

subroutine, the PC manipulates the program transfer by

loading the address corresponding to each instruction.

The conditional skip is activated by instruction. Once the

condition is met, the next instruction, fetched during the

current instruction execution, is discarded and a dummy

cycle replaces it to retrieve the proper instruction. Other-

wise proceed with the next instruction.

The lower byte of the program counter (PCL) is a read-

able and writeable register (06H). Moving data into the

PCL performs a short jump. The destination will be

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

P C

S y s t e m C l o c k o f M C U

( f O S C / 2 )

Execution Flow

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