HT36A4 datasheet(7/38 Pages) HOLTEK

7 / 38 page

HT36A4

Rev. 1.10

March 12, 2007

within 256 locations.

Once a control transfer takes place, an additional

dummy cycle is required.

Program ROM

HT36A4 provides 15 address lines WA[14:0] to read the

Program ROM which is up to 512K bits, and is com-

monly used for the wavetable voice codes and the pro-

gram memory. It provides two address types, one type is

for program ROM, which is addressed by a bank pointer

PF1~0 and a 13-bit program counter PC 12~0; and the

other type is for wavetable code, which is addressed by

the start address ST10~0. On the program type,

WA14~0=PF1~0

´213+ PC12~0. On the wave table

ROM type, WA15~0=ST10~0

´25.

Program Memory

- ROM

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

8192

´16 bits, addressed by the bank pointer, program

counter and table pointer.

Certain locations in the program memory of each bank

are reserved for special usage:

· Location 000H on bank0

This area is reserved for the initialization program. Af-

ter chip reset, the program always begins execution at

location 000H on bank0.

· Location 008H

This area is reserved for the Timer Counter 0 interrupt

service program on each bank. If timer interrupt results

from a Timer Counter 0 overflow, and if the interrupt is

enabled and the stack is not full, the program begins ex-

ecution at location 008H corresponding to its bank.

· Location 00CH

This area is reserved for the Timer Counter 1 interrupt

service program on each bank. If a timer interrupt re-

sults from a Timer Counter 1 overflow, and if the inter-

rupt is enabled and the stack is not full, the program

begins execution at location 00CH corresponding to

its bank.

· Table location

Any location in the ROM space can be used as

look-up tables. The instructions TABRDC [m] (the cur-

rent page, 1 page=256 words) and TABRDL [m] (the

last page) transfer the contents of the lower-order

byte to the specified data memory, and the

higher-order byte to TBLH (08H). Only the destination

of the lower-order byte in the table is well-defined, the

higher-order byte of the table word are transferred to

the TBLH. The Table Higher-order byte register

(TBLH) is read only. The Table Pointer (TBLP) is a

read/write register (07H), which indicates the table lo-

cation. Before accessing the table, the location must

be placed in TBLP. The TBLH is read only and cannot

be restored. If the main routine and the ISR (Interrupt

Service Routine) both employ the table read instruc-

tion, the contents of the TBLH in the main routine are

likely to be changed by the table read instruction used

in the ISR. Errors can occur. In this case, using the ta-

Mode

Program Counter

*14 *13 *12

*11

*10

Initial Reset

000000000000

Timer/Event Counter 0 Overflow

000000001000

Timer/Event Counter 1 Overflow

000000001100

Skip

Program Counter+2

Loading PCL

PF1 PF0 *12 *11 *10

@7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch

PF1 PF0 #12 #11 #10

Return from Subroutine

PF1 PF0 S12 S11 S10 S9

Program Counter

Note:

*12~*0: Bits of Program Counter

@7~@0: Bits of PCL

#12~#0: Bits of Instruction Code

S12~S0: Bits of Stack Register

@7~@0: Bits of PCL

PF1~PF0: Bits of Bank Register

0 0 0 0 H

0 0 0 8 H

T i m e r C o u n t e r 0 i n t e r r u p t s u b r o u t i n e

P r o g r a m

R O M

1 6 b i t s

L o o k - u p t a b l e ( 2 5 6 w o r d s )

n 0 0 H

L o o k - u p t a b l e ( 2 5 6 w o r d s )

1 F F F H

N o t e : n r a n g e s f r o m 0 0 t o 1 F .

n F F H

T i m e r C o u n t e r 1 i n t e r r u p t s u b r o u t i n e

0 0 0 C H

D e v i c e i n i t i a l i z a t i o n p r o g r a m

Program Memory for Each Bank

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