HT36A4 datasheet(10/38 Pages) HOLTEK

10 / 38 page

HT36A4

Rev. 1.10

March 12, 2007

All these kinds of interrupt have a wake-up capability. As

an interrupt is serviced, a control transfer occurs by push-

ing the program counter onto the stack and then branch-

ing to subroutines at specified locations in the program

memory. Only the program counter is pushed onto the

stack. If the contents of the register and Status register

(STATUS) are altered by the interrupt service program

which may corrupt the desired control sequence, then the

programmer must save the contents first.

The internal Timer Counter 0 interrupt is initialized by set-

ting the Timer Counter 0 interrupt request flag (T0F; bit 5

of INTC), caused by a Timer Counter 0 overflow. When

the interrupt is enabled, and the stack is not full and the

T0F bit is set, a subroutine call to location 08H will occur.

The related interrupt request flag (T0F) will be reset and

the EMI bit cleared to disable further interrupts.

The Timer Counter 1 interrupt is operated in the same

manner as Timer Counter 0. The related interrupt con-

trol bits ET1I and T1F of the Timer Counter 1 are bit 3

and bit 6 of the INTC respectively.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, the RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

Timer Counter 0 overflow

08H

Timer Counter 1 overflow

0CH

Once the interrupt request flags (T0F, T1F) are set, they

will remain in the INTC register until the interrupts are

serviced or cleared by a software instruction. It is recom-

mended that a program does not use the

²CALL subrou-

tine

² within the interrupt subroutine. Because interrupts

often occur in an unpredictable manner or need to be

serviced immediately in some applications, if only one

stack is left and enabling the interrupt is not well con-

trolled, once the

²CALL subroutine² operates in the inter-

rupt subroutine, it may damage the original control

sequence.

Oscillator Configuration

The HT36A4 provides two types of oscillator circuit for

the system clock, i.e., RC oscillator and crystal oscilla-

tor. No matter what type of oscillator, the signal divided

by 2 is used for the system clock (fSYS=fOSC/2). The

HALT mode stops the system oscillator and ignores ex-

ternal signal to conserve power. If the RC oscillator is

used, an external resistor between OSC1 and VSS is re-

quired, and the range of the resistance should be from

30k

W to 680kW. The system clock, divided by 4 (fOSC2=

fSYS/4=fOSC/8), is available on OSC2 with pull-high re-

sistor, which can be used to synchronize external logic.

The RC oscillator provides the most cost effective solu-

tion. However, the frequency of the oscillation may vary

with VDD, temperature, and the chip itself due to pro-

cess variations. It is therefore, not suitable for timing

sensitive operations where accurate oscillator fre-

quency is desired.

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through

carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

3OV

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-

est-order bit, or vice versa; otherwise OV is cleared.

PDF

PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by

executing the HALT instruction.

5TO

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by

a WDT time-out.

6~7

Unused bit, read as

²0²

Status (0AH) Register

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