HT36A4 datasheet(8/38 Pages) HOLTEK

8 / 38 page

HT36A4

Rev. 1.10

March 12, 2007

ble read instruction in the main routine and the ISR si-

multaneously should be avoided. However, if the table

read instruction has to be applied in both the main rou-

tine and the ISR, the interrupt should be disabled prior

to the table read instruction. It will not be enabled until

the TBLH has been backed up. All table related in-

structions need 2 cycles to complete the operation.

These areas may function as normal program mem-

ory depending upon user requirements.

· Bank pointer

The program memory is organized into 4 banks and

each bank into 8192

´16 bits of program ROM. PF[1~0]

is bank pointer. After an instruction has been executed

to write data to the PF register to select a different

bank, note that the new bank will not be selected imme-

diately. It is not until the following instruction has com-

pleted execution that the bank will be actually selected.

It should be note that the PF register is write only.

Wavetable ROM

The ST[10~0] is used to defined the start address of

each sample on the wavetable and read the waveform

data from the location. HT36A4 provides 16 output ad-

dress lines from WA[15~0], the ST[10~0] is used to lo-

cate the major 16 bits i.e. WA[15~5] and the undefined

data from WA[4~0] is always set to 00000b. So the start

address of each sample have to be located at a multiple

of 32. Otherwise, the sample will not be read out cor-

rectly because it has a wrong starting code.

Stack Register

- Stack

This is a special part of the memory which is used to

save the contents of the program counter (PC) only. The

stack is organized into 8 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledgment, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the stack pointer will point to

the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a CALL is subse-

quently executed, a stack overflow occurs and the first

entry will be lost (only the most recent eight return ad-

dress are stored).

Data Memory

- RAM

The data memory is designed with 256

´8 bits. The data

memory is divided into three functional groups: special

function registers, wavetable function register, and gen-

eral purpose data memory (208

´8). Most of them are

read/write, but some are read only.

The unused space before 30H is reserved for future ex-

panded usage and reading these locations will return

the result 00H. The general purpose data memory, ad-

dressed from 30H to FFH, is used for data and control

information under instruction command.

All data memory areas can handle arithmetic, logic, in-

crement, decrement and rotate operations directly. Ex-

cept for some dedicated bits, each bit in the data

memory can be set and reset by the SET [m].i and CLR

[m].i instructions, respectively. They are also indirectly

accessible through Memory pointer registers

(MP0:01H, MP1:03H).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] access data memory pointed

to by MP0 (01H) and MP1 (03H) respectively. Reading

location 00H or 02H directly will return the result 00H.

And writing directly results in no operation.

The function of data movement between two indirect ad-

dressing registers, is not supported. The memory

pointer registers, MP0 and MP1, are 8-bit register which

can be used to access the data memory by combining

corresponding indirect addressing registers.

Instruction(s)

Table Location

*14

*13

*12

*11

*10

TABRDC [m]

P14

P13

P12

P11

P10

TABRDL [m]

P14

P13

11111

Table Location

Note:

*12~*0: Bits of table location

@7~@0: Bits of table pointer

P12~P8: Bits of current Program Counter

P14~P13: Bits of bank PF1~PF0

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