LPC2470 datasheet(2/72 Pages) PHILIPS

2 / 72 page

LPC2470_0

Preliminary data sheet

Rev. 00.01 — 5 October 2007

2 of 72

NXP Semiconductors

LPC2470

Fast communication chip

EMC provides support for asynchronous static memory devices such as RAM, ROM

and flash, as well as dynamic memories such as Single Data Rate SDRAM.

Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I2S,

and SD/MM interface as well as for memory-to-memory transfers.

Serial Interfaces:

Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB bus.

USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and

associated DMA controller.

Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

CAN controller with two channels.

SPI controller.

Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.

Three I2C-bus interfaces (one with open-drain and two with standard port pins).

I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

Other peripherals:

SD/MMC memory card interface.

160 General purpose I/O pins with configurable pull-up/down resistors.

10-bit ADC with input multiplexing among 8 pins.

10-bit DAC.

Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

Two PWM/timer blocks with support for three-phase motor control. Each PWM has

an external count inputs.

Real-Time Clock (RTC) with separate power domain. Clock source can be the RTC

oscillator or the APB clock.

2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

Single 3.3 V power supply (3.0 V to 3.6 V).

4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

the system clock.

Three reduced power modes: idle, sleep, and power-down.

Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0

and PORT2 can be used as edge sensitive interrupt sources.

Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).

Two independent power domains allow fine tuning of power consumption based on

needed features.

Each peripheral has its own clock divider for further power saving. These dividers help

reduce active power by 20 % to 30 %.

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