5

HV230/HV232

D0

D1

D2

D3

D4

D5

D6

D7

LE

CL

SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

LL

L

OFF

HL

L

ON

L

L

L

OFF

HL

L

ON

X

X

X

X

X

X

X

X

H

L

HOLD PREVIOUS STATE

X

X

X

X

X

X

X

X

X

H

OFF OFF OFF OFF OFF OFF OFF OFF

Truth Table

Notes:

1. The eight switches operate independently.

2. Serial data is clocked in on the L to H transition CLK.

3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is

low the shift register data flows through the latch.

5. Shift register clocking has no effect on the switch states if LE is H.

6. The clear input overrides all other inputs.

DATA

IN

CLOCK

DATA

OUT

D

N + 1

N

N - 1

D

D

50%

50%

50%

50%

50%

50%

50%

50%

50%

OUT

(TYP)

V

OFF

ON

CLR

t

WCL

90%

10%

t

OFF

DD

SD

ON

t

tt

t

t

h

WLE

SU

t

LE

Logic Timing Waveforms