HT48R53 datasheet(14/35 Pages) HOLTEK

14 / 35 page

HT48R52/HT48R53

Rev. 1.20

December 6, 2005

The states of the registers is summarized in the table.

Reset

(Power On)

WDT Time-out

(Normal Operation)

RES Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

MP0

1xxx xxxx

1uuu uuuu

MP1

1xxx xxxx

1uuu uuuu

ACC

xxxx xxxx

uuuu uuuu

PCL

0000 0000

TBLP

xxxx xxxx

uuuu uuuu

TBLH

(HT48R52)

--xx xxxx

--uu uuuu

TBLH

(HT48R53)

-xxx xxxx

-uuu uuuu

STATUS

--00 xxxx

--1u uuuu

--uu uuuu

--01 uuuu

--11 uuuu

INTC

--00 -000

--uu -uuu

TMR

xxxx xxxx

uuuu uuuu

TMRC

00-0 1000

uu-u uuuu

1111 1111

uuuu uuuu

PAC

1111 1111

uuuu uuuu

1111 1111

uuuu uuuu

PBC

1111 1111

uuuu uuuu

1111 1111

uuuu uuuu

1111 1111

uuuu uuuu

1111 1111

uuuu uuuu

MODE

---0 ---0

---u ---u

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Timer/Event Counter

Timer/event counter (TMR) is implemented in the

microcontroller. The timer/event counter contains an 8-bit

programmable count-up counter and the clock may come

from an external source or from the system clock/4 or fSP.

The fSP clock source is implemented by a WDT OSC, an

external 32768Hz (fRTC) or an instruction clock (system

clock divided by 4), determined by options, if one of

these three source is selected, it will be first divided by

16 (4-stage), and then divided by TMRC prescaler

(8-stage) to get an fSP output period. By using the TMRC

prescaler, longer time-out periods can be realized. Writ-

ing data to PSC2, PSC1, PSC0 can give different fSP

output periods.

Using internal clock sources, there are 2 reference

time-bases for the timer/event counter. The internal

clock source can be selected as coming from fSYS/4 or

fSP by options. Using an external clock input allows the

user to count external events, measure time intervals or

pulse widths, or generate an accurate time base. While

using the internal clock allows the user to generate an

accurate time base.

There are two registers related to the timer/event coun-

ter; TMR ([0DH]) and TMRC ([0EH]). Two physical reg-

isters are mapped to TMR location, writing TMR makes

the starting value be placed in the timer/event counter

preload register and reading TMR retrieves the contents

of the timer/event counter. The TMRC is a timer/event

counter control register which defines some options.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the fINT clock or RTC

clock. The pulse width measurement mode can be used

to count the high or low-level duration of the external sig-

nal. The counting is based on the fINT clock or RTC

clock.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFH. Once over-

flow occurs, the counter is reloaded from the timer/event

counter preload register at the same time generates the

interrupt request flag (TF; bit 5 of the INTC).

HT48R53 Datasheet(PDF) 14 Page - Holtek Semiconductor Inc

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