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HT48R53 Datasheet(PDF) 17 Page - Holtek Semiconductor Inc

Part # HT48R53
Description  I/O Type 8-Bit MCU
PDF  35 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT48R53 Datasheet(HTML) 17 Page - Holtek Semiconductor Inc

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HT48R52/HT48R53
Rev. 1.20
17
December 6, 2005
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
Low Voltage Reset
- LVR
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
The LVR includes the following specifications:
· The low voltage (0.9V~V
LVR) has to remain in their
original state for more than 1ms. If the low voltage
state does not exceed 1ms, the LVR will ignore it and
do not perform a reset function.
· The LVR uses the
²OR² function with the external
RES signal to perform a chip reset.
The relationship between VDD and VLVR is shown below.
Note:
VOPR is the voltage range for proper chip opera-
tion at 4MHz system clock.
V D D
5 . 5 V
V L V R
0 . 9 V
0 V
R e s e t S i g n a l
R e s e t
* 1
* 2
N o r m a l O p e r a t i o n
R e s e t
L V R D e t e c t V o l t a g e
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained for more than 1ms, therefore a 1ms delay is provided before
entering the reset mode.
5 . 5 V
3 . 0 V
2 . 2 V
0 . 9 V
V D D
V O P R
V L V R
5 . 5 V
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure having
a proper functioning system.
Items
Options
1
PA7~PA0 bit wake-up enable or disable (by bit)
2
PA, PB, PC, PD, PE pull-high enable or disable (by port)
3
WDT clock source: WDT oscillator or fSYS/4 or 32768Hz oscillator
4
WDT enable or disable
5
CLRWDT instructions: 1 or 2 instructions
6
Timer/event counter clock sources: fSYS/4 or fSP
7
PB0, PB1: normal I/O or Buzzer function
8
Buzzer frequency: fS/2, fS//4, fS/8, fS//16
9
LVR enable or disable



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