6 / 9 page
CY2285
6
Switching Characteristics[8] Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All
Output Duty Cycle[9]
t1 = t1A ÷ t1B
45
50
55
%
t2
CPUCLK
CPU Clock Rising and
Falling Edge Rate
Between 0.4V and 2.0V
1.0
4.0
V/ns
t2
PCICLK
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t2
REF
REF Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V
0.4
1.6
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V
0.4
1.6
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V
100
175
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.5
4.0
ns
t7
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
250
ps
t7
EPCICLK,
PCICLK
EPCI-PCI Clock Skew[7]
Measured at 1.5V
1.0
4.0
ns
t10
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V
700
ps
t11
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
t12
CPUCLK,
PCICLK
Power-up Time
CPU and PCI clock stabilization from
power-up
3
ms
t13
CPUCLK,
PCICLK
/4 Frequency Slew
Time[7]
Time for CPU, EPCI, and PCI clock
frequency to change from f to f/4 after
select input change
10
25
cycles
Notes:
8.
All parameters specified with loaded outputs.
9.
Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
