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CY2285
3
Pin Summary: CY2285-2
Name
Pins
Description
VDD
8, 13, 19, 28
3.3V Power supply
VDDCPU
25
2.5V Power supply
VSS
7, 15, 21, 22
Ground
XTALIN[3]
2
Reference crystal input
XTALOUT[3]
3
Reference crystal feedback
PCI_STOP
20
Active LOW control input to stop PCI clocks
CPU_STOP
18
Active LOW control input to stop CPU clocks
PWR_DWN
17
Active LOW control input to power down device
DIV4
16
Active LOW control input to enable divide-by-four option on
CPU and PCI clocks
CPUCLK[0:1]
23, 24
2.5V CPU clock outputs
PCICLK[1:5]
5, 6, 9, 10, 11
3.3V PCI clock outputs
PCICLK_F
4
3.3V Free-running PCI clock output
EPCICLK
12
3.3V Early PCI clock output (Not Free-running)
REF0
1
3.3V 14.318-MHz reference clock output
REF1
27
3.3V 14.318-MHz reference clock output
USBCLK/SEL100/66
14
3.3V 48-MHz USB clock output or select input and frequency
select strap option (use 10-k
Ω external strap resistor)
Strap LOW = 66.6-MHz CPU Frequency
Strap HIGH = 100-MHz CPU Frequency
SPREAD
26
Active LOW control input to enable Spread Spectrum
Actual Clock Frequency Values
Clock Output
Target Frequency
(MHz)
Actual Frequency
(MHz)
PPM
CPUCLK
66.67
66.654
–240
CPUCLK
100
99.77
–2300
USB 48-MHz
48
48.008
+167
Power Management Logic
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
PCICLK
PCICLK_F
Other
Clocks
Osc.
PLLs
X
X
0
Low
Low
Low
Low
Off
Off
0
0
1
Low
Low
Running
Running
Running
Running
0
1
1
Low
Running
Running
Running
Running
Running
1
0
1
Running
Low
Running
Running
Running
Running
1
1
1
Running
Running
Running
Running
Running
Running
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