100-MHz Pentium®II Clock Synthesizer/Driver
with Spread Spectrum for Mobile PCs
CY2285
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 18, 2000
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution for Pentium® II, and other sim-
ilar processor-based motherboards
— Two CPU clocks at 2.5V up to 100 MHz
— Six synchronous PCI clocks, one free-running
— Two 3.3V Reference clocks at 14.318 MHz
— One 3.3V USB clock running at 48 MHz
— One 3.3V USB/IO clock running at 48 MHz/24 MHz
• Spread Spectrum clocking for EMI control
• 1.5–4.0 ns delay between CPU and PCI clocks
• Power-down, CPU stop and PCI stop pins
• Low skew outputs,
≤ 175 ps between CPU clocks
• Early PCI clock leads PCI by 1–4 ns (-2 option)
•DIV4 allows dynamic shifting of CPU and PCI clocks
from the default frequency to default/4 (-2 option)
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• Available in space-saving 28-pin SSOP package
Functional Description
The CY2285 is a clock synthesizer/driver for Pentium II, or
other similar processor-based mobile PCs requiring up to
100-MHz support. The CY2285 outputs two CPU clocks at
2.5V. There are six PCI clocks, running at one-half or one-third
the CPU clock frequency of 66.6 MHz and 100 MHz respec-
tively. One of the PCI clocks is free-running. Additionally, the
part outputs two 3.3V reference clocks at 14.318 MHz.
The CY2285 provides incorporates the Intel®-defined spread
spectrum features. It provides a –0.6% downspread on the
CPU and PCI clocks, which can help reduce EMI in certain
high-speed systems.
The CY2285 possesses power-down, CPU stop, and PCI stop
pins for power management control. The signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.
The CY2285-2 features an early PCI clock which leads the
other PCI clocks by 1–4 ns. The CY2285-2 also features a
DIV4 pin which allows for dynamic shifting of CPU and PCI
clocks from the default frequency to the default/4.
Notes:
1.
One free-running PCI clock.
2.
One early PCI clock.
CY2285 Selector Guide
Clock Outputs
CY2285-1
CY2285-2
CY2285-3
CPU (66,
100 MHz)
222
PCI (CPU/2,
CPU/3 MHz)
6[1]
7[1, 2]
6[1]
Ref. (14.318 MHz)
2
2
1
USB (48 MHz)
1
1
1
USB/IO (48
MHz/24 MHz se-
lectable)
1N/A
1
CPU-PCI delay
1.5–4.0 ns
1.5–4.0 ns
1.5–4.0 ns
EPCI-PCI delay
N/A
1.0–4.0 ns
N/A
Spread Spectrum
–0.6%
Downspread
–0.6%
Downspread
–0.6%
Downspread
Intel and Pentium are registered trademarks of Intel Corporation.
Logic Block Diagram
EPROM
XTALOUT
XTALIN
14.318
MHz
OSC.
CPU
PLL
Delay
REF1/SEL48
CPUCLK [0–1]
VDDCPU
PCICLK [1-5]
EPCICLK (-2 option)
STOP
STOP
LOGIC
LOGIC
CPU_STOP
DIV4
Divider
PCI_STOP
VDDPCI
VDDPCI
VDDREF
REF0/SPREAD
SYS
PLL
USBCLK
VDD48
USB_IOCLK/TS (-1 option)
VDD48
PCICLK_F
VDDPCI
PWR_DWN
USBCLK/SEL100/66 (-2 option)
/4
SPREAD (-2,-3 option)
REF0 (-2 option)
REF1 (-2,-3 option)
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