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 2007 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1116

Application Information

Overview

The SC1116 linear controller is designed to meet the

JEDEC specifications for termination of DDR-SDRAM.

Double Data Rate (DDR) memory is clocked at the same

speed as older SDRAM (synchronous dynamic random

access memory), yet handles twice the amount of data

by using the rising and falling edge of the clock signal for

data transfers. Another difference is that DDR memory

requires 2.5V instead of 3.3V used by standard SDRAM.

The other feature that separates DDR memory from a

conventional type is employment of the V

voltage. Main requirements for the V

track variations of V

current, and absorb (sink) current.

The SC1116 controller offers a low cost solution for DDR

termination voltage regulation by using external pass el-

ements (MOSFETs). Having the flexibility of choosing the

MOSFETs allows for optimization on the basis of cost/

size/performance of the specific application.

Test Circuit & Waveforms

The test circuit is shown below in Figure 1.

Note that V

inaccuracy caused by resistor divider.

Figure 1.

REF

3

DRVL

4

VCC

1

FB

5

GND

2

DRVH

6

U1

SC1116

C3

0.1uF

C2

1uF

C4

4.7nF

C5

4.7nF

C6

270uF

R3

1k

R4

1k

Q1

IR37 14

Q2

IR37 14

VTT=1.25Vtyp

C1

100uF

22m

32m

2xIsin k

Isin k

Po wer

Electronic

Cu rrent

Su pp ly

Loa d

Pu lse loa d, dc=50%

Iso urce/ Isink

Pro be

VDDQ=2.5V

Vcc=5V

Vref=1.25V

+/-3A

0A to 6A Step

3A Isource