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GL860 Datasheet(PDF) 13 Page - GENESYS LOGIC |
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GL860 Datasheet(HTML) 13 Page - GENESYS LOGIC |
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13 / 24 page ![]() GL860 USB 2.0 PC Camera Controller ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 13 3.3 Pin Descriptions Table 3.3 - 100-Pin QFP Pin Descriptions Pin Name Pin# Type Description DVDD 27,39,77,81 P 1.8V core power CMS_DAT0~9 20,21,83~86, 2~5 I Sensor data bit 0~9 FSH_OEB 6 I Read strobe of Output enable for flash memory. Low active FSH_WEB 7 I Write strobe of Write enable for flash memory. Low active FSH_ADR0~15 8,9,14~17, 37,38,71~74 , 93~96 I/O Port 0 and Port 2 for Address of flash memory GPIO0~14 10~13,57~62, 87,88,31,32,34 I/O (pd) GPIO pins bit 0~14 GND 26,40,41,42, 46,47,56,78, 82,99 P Ground HRST_ 30 I (pu) Hardware reset, low active EXTCPU 33 I Use external CPU mode for firmware development. AVDD33 43,49,50 P 3.3V analog power DM 44 I/O USB D- DP 45 I/O USB D+ RREF 48 A Reference R DVDD33 53,79,100 P 3.3V power X1 54 I 12M crystal in X2 55 I/O 12M crystal out FSH_DAT0~7 89,90,91,92, 63,64,67,68 I/O Data bus of flash memory CMS_CLK 75 I/O Sensor clock TEST 76 I (pd) Test mode VSYNC 97 I/O Sensor Vsync HSYNC 98 I/O Sensor Hsync NC 1,18,19,22~25, 28,29,35,36, 51,52,65,66, 69,70,80 - No connection |
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