 2001 Microchip Technology Inc.

DS00754A-page 3

AN754

FIGURE 3:

CAN BIT TIMING CONTROL REGISTERS (MCP2510 CNF REGISTERS)

BRP.2

BRP.3

BRP.4

SJW.1

bit 7

bit 0

BRP.5

SJW.0

BRP.0

BRP.1

PRSEG.2

PS1.0

PS1.1

BTLMODE

bit 7

bit 0

PS1.2

SAM

PRSEG.0

PRSEG.1

PHSEG21

---

---

bit 7

bit 0

---

WAKFIL

PHSEG22

---

PHSEG20

SJW<1:0> (Synchronization Jump Width Length as measured in TQ):

11

= 4TQ

10

= 3TQ

01

= 2TQ

00

= 1TQ

111111

.

.

.

.

.

.

000010

000001

000000

BTLMODE (Determines how PS2 is calculated)

1

= PS2 is determined by CNF3.PS2<2:0>

0

= PS2 is the greater of PS1 and the Information Processing Time (IPT)

SAM (Configures the sample point as one sample or three samples

1

= Sample three times per bit

0

= Sample once per bit

PS1<2:0> (Configures Phase Segment 1)

111

= 8TQ

. .

. .

001

= 2TQ

000

= 1TQ

PRSEG<2:0> (Configures the Propagation Segment)

111

= 8TQ

. .

. .

001

= 2TQ

000

= 1TQ

WAKFIL (Enables/Disables the wakeup filter)

1

= Filter enabled

0

= Filter disabled

PS2<2:0> (Configures Phase Segment 2)

111

= 8TQ

. .

. .

001

= 2TQ

000

CNF1

CNF3

CNF2