AN754 datasheet(6/13 Pages) MICROCHIP

6 / 13 page

AN754

DS00754A-page 6

 2001 Microchip Technology Inc.

RESYNCHRONIZATION

Resynchronization is implemented to maintain the ini-

tial synchronization that was established by the hard

synchronization. Without resynchronization, the receiv-

ing nodes could get out of synchronization due to oscil-

lator drift between nodes.

Resynchronization is achieved by implementing a Dig-

ital Phase Lock Loop (DPLL) function which compares

the actual position of a recessive-to-dominant edge on

the bus to the position of the expected edge (within the

SyncSeg) and adjusting the bit time as necessary.

The phase error of a bit is given by the position of the

edge in relation to the SyncSeg, measured in TQ, and

is defined as follows:

• e = 0; the edge lies within the SyncSeg.

• e > 0; the edge lies before the sample point. (TQ

added to PS1).

• e < 0; the edge lies after the sample point of the

previous bit. (TQ subtracted from PS2)

FIGURE 5:

SYNCHRONIZING THE BIT TIME

SyncSeg

PropSeg

PhaseSeg1 (PS1)

PhaseSeg2 (PS2)

Sample

Point

SyncSeg

PropSeg

PhaseSeg1 (PS1)

PhaseSeg2 (PS2)

Sample

Point

SyncSeg

PropSeg

PhaseSeg1 (PS1)

PhaseSeg2 (PS2)

Sample

Point

Nominal Bit Time (NBT)

SJW (PS1)

SJW (PS2)

Nominal Bit Time (NBT)

SJW (PS1)

SJW (PS2)

Actual Bit Time

Resynchronization to a Slower Transmitter (e > 0)

Input Signal

Input Signal (e < 0)

SJW (PS1)

SJW (PS2)

Nominal Bit Time (NBT)

Actual Bit Time

Resynchronization to a Faster Transmitter (e < 0)

Input Signal (e = 0)

No Resynchronization (e = 0)

(e > 0)

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