King Billion Electronics Co., Ltd

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HE83005

HE80000 SERIES

July 28, 2003

8

V3.4

This specification is subject to change without notice. Please contact sales person for the latest version before use.

T2H

T2L

< Timer2 Counter >

Decreases 1

Count To

0xFFFFh

The contents of

T2H and T2L are

almost loaded into

Timer2 immediately

when Timer2 is

enabled after reset.

Auto reload

when Timer2

is underflow

Yes

No

Timer2

Interrupt

Request

T2_INT

9. Watch Dog Timer

Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by

abnormal hardware activities or program execution. WDT needs to be enabled in Mask Option.

MO_WDTE

Function

0

WDT disable

1

WDT enable

To use WDT function, “CLRWDT” instruction needs to be executed in every possible program path

when the program runs normally in order to clears the WDT counter before it overflows, so that the

program can operate normally. When abnormal conditions happen to cause the MCU to divert from

normal path, the WDT counter will not be cleared and reset signal will be generated.

WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is

same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated

in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1

clock has stopped.)