King Billion Electronics Co., Ltd

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HF88M32B

January 16, 2004

4

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use.

Symbol

Pin No.

I/O

Description

RS0~RS2

33, 2, 1

I

Register Select pins RS2 ~ RS0 for accessing ROM data, Address

Counter, as well as extension I/O ports.

P07 ~ P00

3 ~ 10

I/O Bi-directional I/O port P0.

CEn

11

I

The CEn (Chip Enable) input is the device selection and power control

for internal Mask ROM array. Whenever CEn goes high, the internal

Mask ROM will enter standby (power saving) mode and accesses to

internal registers are inhibited. Otherwise, it is in active mode and the

contents of the ROM and registers can be accessed. Please note that only

accesses to the internal registers are inhibited, but the status of I/O

registers are not affected by the CEn pin and will remain unchanged. CEn

is also useful to uniquely select a certain device for applications where

multiple-chip array is required.

GND

12, 31

P

Negative power supply input pin.

OEn

13

I

OEn (Output Enable) is the output control which gates ROM array data,

extension I/O ports, Direction Registers to the data I/O pins D7 ~ D0.

The internal Address Counter will automatically increment by one with

each rising edge of OEn pin in Sequentially Read mode.

VCC

22

P

Postive power supply input pin.

D7 ~ D0

14, 16, 18,

20, 23, 25,

27, 29

I/O The Bi-directional Data I/O pins are used to set starting addresses, set the

Extension I/O Direction and Output Registers, and to output ROM array

data during read operations, contents of I/O Registers and status of input

pins. The D7 ~ D7 float to high-impedance when the chip is deselected

(CEn high) or when the outputs are disabled.

P17 ~ P10

34 ~ 41

I/O Bi-directional I/O port P1.

WEn

42

I

WEn controls writing to internal registers such as the Output Port

Registers, Direction Registers, Address Counter and Data on D7 ~ D0 are

latched on the rising edge of the WE pulse.