King Billion Electronics Co., Ltd

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HF88M32B

January 16, 2004

7

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use.

CEn pin should be held at ‘1’ to conserve the power consumption.

In addition to Data File mode, the device also provides the extension I/O capability. Two I/O ports (P0, P1)

and total 16 pins are provided. The I/O ports can be configured to function as output pin or

high-impedance input pins. Only 14 pins, CEn, WEn, OEn, RS2, RS1, RS0 and D0 ~ D7 are required to

provide the Data File function and full access to two I/O ports.

There are seven internal registers used to provide the functionality of Data file access as well as

Extension I/O capability. These registers are selected by RS2 ~ RS0. All registers are 8-bit wide except

AC2. AC2 ~ AC0 are write-only and constitute the complete 22-bit address counter used as pointer to the

accessed data. While the I/O ports P0, P1, DIR0 and DIR1 can be read as well as written. Their initial

values are as indicated in the following table. When RS2 = ‘0’, the RS1 ~ RS0 are ignored, the address

counter can be loaded or contents of Data File can be read. This is to reduce the required pin needed for

external MCU to interface with the device and also simplify the procedure for loading the address

counter.

The P0, P1, DIR0, and DIR1 are used for extension I/O registers. The P0 and P1 are output registers of

extension I/O and DIR0 and DIR1 are the direction registers that determine the I/O mode of P0 and P1.

Each pin can be configured as output or input mode individually by setting or resetting the corresponding

pin of the DIR registers. Initially, both P0 and P1 are default to input mode at ‘Hi’ state.

The accesses to the internal registers will be inhibited when CEn is ‘1’. However, the status of internal

registers, such as extension I/O ports, will not be affected. For example, if a certain pin is in output mode

and driving ‘Hi’, it will not change when CEn pin goes to ‘1’ state. Therefore, the users are advised to

take care of the power down condition of I/O ports when entering sleep mode to prevent unnecessary

power drain.

RS[2:0]

Symbol

Type

Description

Initial Value

R

Read data by Indirect access

AC2

W

Address latch 2 for A21 ~ A16

“--------“

AC1

W

Address latch 1 for A15 ~ A8

“--------“

0xx

AC0

W

Address latch 0 for A7 ~ A0

“--------“

100

P0

R/W

Port 0 Output Register

“11111111“

101

DIR0

R/W

Direction Register of Port0

“00000000“

110

P1

R/W

Port 1 Output Register

“11111111“

111

DIR1

R/W

Direction Register of Port1

“00000000“

The writing sequence of address counters are AC0 first, AC1 second and AC2 last, once the OEn pin is

active to low, and writing pointer of address counter (AC) will be reset to AC0 and always stay at AC0

until the RS2 is set to “0” and WEn pin has a low to high toggle to increase the writing pointer of address

counter (AC).