UC2856Q datasheet(4/12 Pages) TI

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(4)

Amplifier gain defined as:

G +

DVCOMP

DVCS)

; DVCS * + 0 V 1 V.

UC2856Q

SGLS265 – NOVEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

A = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER SECTION

Input offset voltage

VCM = 2 V

Input bias current

–1

µA

Input offset current

500

Common mode range

VIN = 8 V to 40 V

VIN–2

Open loop gain

VO = 1.2 V to 3 V

100

Unity gain bandwidth

TJ = 25°C

1.5

MHz

CMRR

VCM = 0 V to 38 V,

VIN = 40 V

100

PSRR

VIN = 8 V to 40 V

100

Output sink current

VID = -15 mV

VCOMP = 1.2 V

Output source current

VID = 15 mV

VCOMP = 2.5 V

–0.4

–0.5

High-level output voltage

VID = 50 mV,

RL (COMP) = 15 kΩ

4.3

4.6

4.9

Low-level output voltage

VID = –50 mV,

RL (COMP) = 15 kΩ

0.7

CURRENT SENSE AMPLIFIER SECTION

Amplifier gain

VCS– = 0 V,

CL SS Open(3)(4)

2.5

2.75

V/V

Maximum differential input signal (VCS+– VCS–)

CL SS Open 3,

RL (COMP) = 15 kΩ

1.1

1.2

Input offset voltage

VCL SS = 0.5 V

COMP open(5)

CMRR

VCM = 0 V to 3 V

PSRR

VIN = 8 V to 40 V

Input bias current

VCL SS = 0.5 V,

COMP open(5)

–1

µA

Input offset current

VCL SS = 0.5 V,

COMP open(5)

Input common mode range

Delay to outputs

VEA+ = VREF, EA– = 0 V, CS+ – CS– = 0 V to 1.5 V

120

250

CURRENT LIMIT ADJUST SECTION

Current limit offset

VCS– = 0 V, VCS+ = 0 V,

COMP Open(5)

0.4

0.5

0.6

Input bias current

VEA+ = VREF,

VEA– = 0 V

–10

–30

µA

SHUTDOWN TERMINAL SECTION

Threshold voltage

0.95

1.00

1.05

Input voltage range

Minimum latching current (ICL SS)

(6)3

1.5

Maximum non-latching current (ICL SS)

(7)1.5

0.8

Delay to outputs

VSHUTDOWN = 0 V to 1.3 V

110

OUTPUT SECTION

Collector-emitter voltage

Off-state bias current

VC = 40 V

250

µA

IOUT = 20 mA

0.1

0.5

Output low level voltage

IOUT = 200 mA

0.5

2.6

IOUT = –20 mA

12.5

13.2

Output high level voltage

IOUT = –200 mA

13.1

Rise time

C1 = 1 nF

Fall time

C1 = 1 nF

(3)

Parameter measured at trip point of latch with VEA+ = VREF, VEA- = 0 V.

(5)

Parameter measured at trip point of latch with VEA+ = VREF, VEA- = 0 V.

(6)

Current into CL SS assured to latch circuit into shutdown state.

(7)

Current into CL SS assured not to latch circuit into shutdown state.

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