DEVICES INCORPORATED

LF3321

Horizontal Digital Image Filter

Improved Performance

LOGIC Devices Incorporated

4

Feb 5, 2003 LDS.3321-A

Video Imaging Products

The ALUs double the number of filter taps available, when symmetric coefficient sets are used, by pre-

adding data values which are then multiplied by a common coefficient (see Figure 4). The ALUs can

perform two operations: A+B and B–A. Bit 0 of Configuration Register 0 determines the operation of the

ALUs in Filter A. Bit 0 of Configuration Register 2 determines the operation of the ALUs in Filter B. A+B is

used with even-symmetric coefficient sets. B–A is used with odd-symmetric coefficient sets.

Also, either the A or B operand may be set to 0. Bits 1 and 2 of Configuration Register 0 and Configuration

Register 2 control the ALU inputs in Filters A and B respectively. A+0 or B+0 are used with asymmetric

coefficient sets.

The Interleave/Decimation Registers (I/D Registers), feed the ALU inputs. They allow the device to filter up

to sixteen data sets interleaved into the same data stream without having to separate the data sets. The I/D

Registers should be set to a length equal to the number of data sets interleaved together.

For example, if two data sets are interleaved together, the I/D Registers should be set to a length of two.

Bits 1 through 4 of Configuration Register 1 and Configuration Register 3 determine the length of the I/D

Registers in Filters A and B respectively.

The I/D Registers also facilitate using decimation to increase the number of filter taps. Decimation by N is

accomplished by reading the filter’s output once every N clock cycles. The device supports decimation up to

16:1. With no decimation, the maximum number of filter taps is sixteen. When decimating by N, the number

of filter taps becomes 16N because there are N–1 clock cycles when the filter’s output is not being read. The

extra clock cycles are used to calculate more filter taps.

When decimating, the I/D Registers should be set to a length equal to the decimation factor. For example,

when performing a 4:1 decimation, the I/D Registers should be set to a length of four. When decimation is

disabled or when only one data set (non-interleaved data) is fed into the device, the I/D Registers should

be set to a length of one.

The three multiplexers in the I/D Register data path control how data is routed through the forward and

reverse data paths. The forward data path contains the I/D Registers in which data flows from left to right

in the block diagram in Figure 1. The reverse data path contains the I/D Registers in which data flows from

right to left. In Single or Dual Filter Modes, data is fed from the forward data path to the reverse data path

as follows. When the filter is configured for an even number of taps, data from the last I/D Register in the

forward data path is fed into the first I/D Register in the reverse data path (see Figure 5). When the filter

is configured for an odd number of taps, the data which will appear at the output of the last I/D Register

in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse data path.

Bit 5 in Configuration Register 1 and Configuration Register 3 configures Filters A and B respectively for

an even or odd number of taps.

Functional Description

ALU

I/D Registers

1

2

3

4

5

6

7

8

Even-Tap, Even-Symmetric

Coefficient Set

Odd-Tap, Even-Symmetric

Coefficient Set

1

2

3

4

5

6

7

8

Even-Tap, Odd-Symmetric

Coefficient Set

1

2

3

4

5

6

7

Figure 4. Symmetric Coefficient Set Examples

I/D Registers Data

Path Control