LPC2142 datasheet(17/39 Pages) NXP

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LPC2141_42_44_46_48_3

Product data sheet

Rev. 03 — 19 October 2007

17 of 39

NXP Semiconductors

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

6.11 UARTs

The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and

receive data lines, the LPC2144/46/48 UART1 also provides a full modem control

handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48

introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers

to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz.

In addition, auto-CTS/RTS ﬂow-control functions are fully implemented in hardware

(UART1 in LPC2144/46/48 only).

6.11.1 Features

• 16 B Receive and Transmit FIFOs

• Register locations conform to 16C550 industry standard

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values

• Transmission FIFO control enables implementation of software (XON/XOFF) ﬂow

control on both UARTs

• LPC2144/46/48 UART1 equipped with standard modem interface signals, this module

also provides full support for hardware ﬂow control (auto-CTS/RTS)

6.12 I2C-bus serial I/O controller

The LPC2141/42/44/46/48 each contain two I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory)). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s

(Fast I2C-bus).

6.12.1 Features

• Compliant with standard I2C-bus interface

• Easy to conﬁgure as master, slave, or master/slave

• Programmable clocks allow versatile rate control

• Bidirectional data transfer between masters and slaves

• Multi-master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

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