LPC2142 datasheet(16/39 Pages) NXP

16 / 39 page

LPC2141_42_44_46_48_3

Product data sheet

Rev. 03 — 19 October 2007

16 of 39

NXP Semiconductors

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

6.9 10-bit DAC

The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The

maximum DAC output voltage is the VREF voltage.

6.9.1 Features

• 10-bit DAC

• Buffered output

• Power-down mode available

• Selectable speed versus power

6.10 USB 2.0 device controller

The USB is a 4-wire serial bus that supports communication between a host and a

number (127 max) of peripherals. The host controller allocates the USB bandwidth to

attached devices through a token based protocol. The bus supports hot plugging,

unplugging, and dynamic conﬁguration of the devices. All transactions are initiated by the

host controller.

The LPC2141/42/44/46/48 is equipped with a USB device controller that enables

12 Mbit/s data exchange with a USB host controller. It consists of a register interface,

serial interface engine, endpoint buffer memory and DMA controller. The serial interface

engine decodes the USB data stream and writes data to the appropriate end point buffer

memory. The status of a completed USB transfer or error condition is indicated via status

registers. An interrupt is also generated if enabled.

A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint

buffer and the USB RAM.

6.10.1 Features

• Fully compliant with USB 2.0 Full-speed speciﬁcation

• Supports 32 physical (16 logical) endpoints

• Supports control, bulk, interrupt and isochronous endpoints

• Scalable realization of endpoints at run time

• Endpoint maximum packet size selection (up to USB maximum speciﬁcation) by

software at run time

• RAM message buffer size based on endpoint realization and maximum packet size

• Supports SoftConnect and GoodLink LED indicator, these two functions share one pin

• Supports bus-powered capability with low suspend current

• Supports DMA transfer on all non-control endpoints (LPC2146/48 only)

• One duplex DMA channel serves all endpoints (LPC2146/48 only)

• Allows dynamic switching between CPU controlled and DMA modes (only in

LPC2146/48)

• Double buffer implementation for bulk and isochronous endpoints

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