LPC2142 datasheet(18/39 Pages) NXP

18 / 39 page

LPC2141_42_44_46_48_3

Product data sheet

Rev. 03 — 19 October 2007

18 of 39

NXP Semiconductors

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I2C-bus can be used for test and diagnostic purposes

6.13 SPI serial I/O controller

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial

interface, designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends a byte of data to the slave, and

the slave always sends a byte of data to the master.

6.13.1 Features

• Compliant with SPI speciﬁcation

• Synchronous, Serial, Full Duplex, Communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

6.14 SSP serial I/O controller

The LPC2141/42/44/46/48 each contain one SSP. The SSP controller is capable of

operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. However, only a single master and a single slave can communicate on

the bus during a given data transfer. The SSP supports full duplex transfers, with data

frames of 4 bits to 16 bits of data ﬂowing from the master to the slave and from the slave

to the master. Often only one of these data ﬂows carries meaningful data.

6.14.1 Features

• Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s

Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• Four bits to 16 bits per frame

6.15 General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

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