TMUX7348F datasheet(39/54 Pages) TI1

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8.3.2.7 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX7348F-EP is constructed on silicon on insulator (SOI) based process where an oxide layer is added

between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The

oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or

current injections. The latch-up immunity feature allows the TMUX7348F-EP to be used in harsh environments.

For more information on latch-up immunity refer to the Using Latch-Up Immune Multiplexers to Help Improve

System Reliability application report.

8.3.2.8 EMC Protection

The TMUX7348F-EP is not intended for standalone electromagnetic compatibility (EMC) protection in industrial

applications. There are three common high voltage transient specifications that govern industrial high voltage

transient specification: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5 (surge immunity). A

transient voltage suppressor (TVS), along with some low-value series current limiting resistors, are required

to prevent source input voltages from going above the rated ±60 V limits.

When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than

both the normal operating range of the input source pins to be protected and any known system common-mode

overvoltage that may be present due to incorrect wiring, loss of power, or short circuit. Figure 8-2 shows an

example of the proper design window when selecting a TVS device.

Region 1 denotes normal operation region of TMUX7348F-EP where the input source voltages stay below the

fault supplies VFP and VFN. Region 2 represents the range of possible persistent DC (or long duration AC

overvoltage fault) presented on the source input pins. Region 3 represents the margin between any known DC

overvoltage level and the absolute maximum rating of the TMUX7348F-EP. The TVS breakdown voltage must

be selected to be less than the absolute maximum rating of the TMUX7348F-EP, but greater than any known

possible persistent DC or long duration AC overvoltage fault to avoid triggering the TVS inadvertently. Region

4 represents the margin system designers must impose when selecting the TVS protection device to prevent

accidental triggering of ESD cells of the TMUX7348F-EP.

Normal Operation

Fault Voltage

Supply VFP

System

Overvoltage

Protection Window

Device Absolute

Max Rating

Internal ESD

Trigger Voltage

TVS

Breakdown

Voltage

Fault Voltage

Supply VFN

0 V

Overvoltage

Protection Window

TVS

Breakdown

Voltage

System

Overvoltage

Device Absolute

Max Rating

Internal ESD

Trigger Voltage

Figure 8-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device

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TMUX7348F-EP

SCDS461A – NOVEMBER 2023 – REVISED JANUARY 2025

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