All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

D

0

●

●

●

●

●

●

●

●

●

●

Configurable UART

ver 2.07

OVERVIEW

The D16450 is a soft Core of a Universal

Asynchronous Receiver/Transmitter (UART)

functionally

identical

to

the

TL16C450.

D16450 performs serial-to-parallel conversion

on data characters received from a peripheral

device or a MODEM, and parallel-to-serial

conversion on data characters received from

the CPU. The CPU can read the complete

status of the UART at any time during the

functional

operation.

Status

information

reported includes the type and condition of the

transfer operations being performed by the

UART, as well as any error conditions (parity,

overrun, framing, or break interrupt). D16450

includes a programmable baud rate generator

that is capable of dividing the timing reference

producing a 16 × clock for driving the internal

transmitter logic. Provisions are also included

to use this 16 × clock to drive the receiver

logic. The D16450 has complete MODEM

control capability, and a processor-interrupt

system. Interrupts can be programmed to the

user's requirements, minimizing the computing

required to handle the communications link.

The separate BAUD CLK line allows to set an

exact transmission speed, while the UART

internal logic is clocked with the CPU

frequency

The core is perfect for applications, where the

UART Core and microcontroller are clocked

by the same clock signal and are implemented

inside the same ASIC or FPGA chip, as well

as for standalone implementation, where

several

UARTs

are

required

to

be

implemented inside a single chip, and driven

by some off-chip devices. Thanks to universal

interface D16450 core implementation and

verification are very simply, by eliminating a

number of clock trees in complete system.

KEY FEATURES

Software compatible with 16450 UART

Configuration capability

Separate configurable BAUD clock line

Majority Voting Logic

Adds or deletes standard asynchronous

communication bits (start, stop, and parity)

to or from the serial data

In UART mode receiver and transmitter

are double buffered to eliminate a need for

precise synchronization between the CPU

and serial data

Independently controlled transmit, receive,

line status, and data set interrupts

False start bit detection

16 bit programmable baud generator

MODEM control functions (CTS, RTS,

DSR, DTR, RI, and DCD)