All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environment

NCSim automatic simulation macros

ModelSim automatic simulation macros

Active-HDL automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, minor and

major versions changes

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Delivery the documentation updates

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Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implementa-

tion. It also permits FPGA prototyping before

ASIC production.

Unlimited Designs

license allows using IP Core

in unlimited number of FPGA bitstreams and

ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

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Single Design license for

VHDL, Verilog source code called HDL Sour-

ce

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Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Designs

DESIGN FEATURES

PROGRAM MEMORY:

The DP80C51 soft core is dedicated for

operation with Internal and External Pro-

gram Memory. Internal Program Memory

can be implemented as:

ROM located in address range between

0x0000

÷ (ROM

RAM located in address range between

External Program Memory can be im-

plemented as ROM or RAM located in ad-

INTERNAL DATA MEMORY:

The DP8C051 can address Internal Data

Memory of up to 256 bytes The Internal

Data Memory can be implemented as Sin-

gle-Port synchronous RAM.

EXTERNAL DATA MEMORY:

The DP80C51 soft core can address up

to 64 kB of External Data Memory.

USER

Up to 104 External (user) Special Func-

tion Registers (ESFRs) may be added to

the DP80C51 design. ESFRs are memory

mapped into Direct Memory between ad-

dresses 0x80 and 0xFF in the same man-

ner as core SFRs and may occupy any ad-

dress that is not occupied by a core SFR.

WAIT STATES SUPPORT:

The DP80C51 soft core is dedicated for

operation with wide range of Program and

Data memories. Slow Program and Exter-

nal Data memory may assert a memory

WAIT signal to hold up CPU activity for re-

quired period of time.