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Transfer Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two

bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit,

which selects an active high or active low clock and has no significant effect on the transfer format.

The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats.

The clock phase and polarity should be identical for the master SPI device and the communicating

slave device. In some cases, the phase and polarity are changed between transfers to allow a

master device to communicate with peripheral slaves having different requirements. The flexibility

of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial

peripheral.

6

6

5

5

4

4

3

3

2

21

1LSB

MSB

MSB

LSB

1

2

3

45

67

8

SC K CYC LE#

SC K (C PO L =0)

SC K (C PO L=1)

MO SI

MISO

SS

6

6

5

5

4

4

3

3

2

21

1LSB

MSB

MSB

LSB

1

2

3

45

67

8

SC K CY CLE #

SC K (C P O L =0)

SC K (C P O L =1)

MO SI

MISO

SS