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D

Serial Peripheral Interface – Master/Slave

ver 2.07

OVERVIEW

The DSPI is a fully configurable SPI mas-

ter/slave device, which allows user to config-

ure polarity and phase of serial clock signal

SCK.

The DSPI allows the microcontroller to

communicate with serial peripheral devices. It

is also capable of interprocessor communica-

tions in a multi-master system. A serial clock

line (SCK) synchronizes shifting and sampling

of the information on the two independent se-

rial data lines. DSPI data are simultaneously

transmitted and received.

The DSPI is a technology independent de-

sign that can be implemented in a variety of

process technologies.

The DSPI system is flexible enough to in-

terface directly with numerous standard prod-

uct peripherals from several manufacturers.

The system can be configured as a master or

a slave device. Data rates as high as CLK/4.

Clock control logic allows a selection of clock

polarity and a choice of two fundamentally

different clocking protocols to accommodate

most available synchronous serial peripheral

devices. When the SPI is configured as a

master, software selects one of eight different

bit rates for the serial clock.

The DSPI automatically drive selected by

SSCR (Slave Select Control Register) slave

select outputs (SS7O – SS0O), and address

SPI slave device to exchange serially shifted

data. Error-detection logic is included to sup-

port interprocessor communications. A write-

collision detector indicates when an attempt is

made to write data to the serial shift register

while a transfer is in progress. A multiple-

master mode-fault detector automatically dis-

ables DSPI output drivers if more than one

SPI devices simultaneously attempts to be-

come bus master.

DSPI is fully customizable, which means it

is delivered in the exact configuration to meet

users’ requirements. There is no need to pay

extra for not used features and wasted silicon.

It includes fully automated testbench with

complete set of tests

allowing easy package

validation at each stage of SoC design flow.

APPLICATIONS

KEY FEATURES

○

Master and Multi-master operations

○

8 SPI slave select lines

○

System error detection

○

Interrupt generation

○

Supports speeds up ¼ of system clock