TMP86CM29BUG datasheet(68/196 Pages) TOSHIBA

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Page 54

5. I/O Ports

5.3 Port P3 (P33 to P30)

TMP86CM29BUG

5.3 Port P3 (P33 to P30)

Port P3 is a 4-bit input/output port.

It is also used as a timer/counter input/output, divider output.

When used as a timer/counter output or divider output, respective output latch (P3DR) should be set to “1”.

It can be selected whether output circuit of P3 port is C-MOS output or a sink open drain individually, by setting

P3OUTCR. When a corresponding bit of P3OUTCR is “0”, the output circuit is selected to a sink open drain and

when a corresponding bit of P3OUTCR is “1”, the output circuit is selected to a C-MOS output. When used as an

input port or timer/counter input, respective output control (P3OUTCR) should be set to “0” after P3DR is set to “1”.

During reset, the P3DR is initialized to “1”, and the P3OUTCR is initialized to “0”.

P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address.

When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD reg-

ister should be read. If a read instruction is executed for port P3, read data of bits 7 to 4 are unstable.

Figure 5-4 Port P3

Port P3 control register

P3DR

(0003H)

R/W

543

P33

PWM6

PDO6

PPG6

TC6

P32

PWM4

PDO4

PPG4

TC4

P31

PWM3

PDO3

TC3

P30

DVO

(Initial value: **** 1111)

P3OUTCR

(0004H)

543

(Initial value: **** 0000)

P3OUTCR

Port P3 output circuit control

(set for each bit individually)

0: Sink open-drain output

1: C-MOS ouput

R/W

P3PRD

(000AH)

Read only

543

P33

P32

P31

P30

Data input (P3PRD)

Data input (P3DR)

Data output (P3DR)

Control output

Control input

STOP

OUTEN

P3OUTCRi

P3OUTCRi input

P3i

Note:i=3

to 0

TMP86CM29BUG Datasheet(PDF) 68 Page - Toshiba Semiconductor

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