EM78452WM datasheet(16/54 Pages) EMC

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EM78452

8-Bit Microcontroller

•

Product Specification (V1.0) 10.18.2007

(This specification is subject to change without further notice)

Refer to the Timer 1 prescaler table for FOSC illustration under the section “Timer 1” on

the subsequent pages.

5.2.5 IOCD (Pull-high Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PU9

/PU8

/PU6

/PU5

The default values of /PU5, /PU6, /PU8, and /PU9 are “1”, which means that the

pull-high function is disabled.

/PU6 and /PU9 are “AND” gating with /PHEN, that is, when each one is written with

a “0”, pull high is enabled.

S7 defines the driving ability of the P70-P72.

0: Normal output

1: Enhances the driving ability of the LED

5.2.6 IOCE (WDT Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ODE

WDTE

SLPC

ROC

/WUE

Bits 7, and 1~2 are not used.

Bit 6 (ODE) Open-drain control bit.

0 : Both P76 and P77 are normally I/O pins.

1 : Both P76 and P77 pins have the open-drain function inside.

The ODE bit can be read and written to.

Bit 5 (WDTE) Control bit used to enable the Watchdog timer.

The WDTE bit can be used only if ENWDT, the Code Option bit, is "1." If the

ENWDT bit is "1," then WDT can be disabled / enabled by the WDTE bit.

0: Disable WDT

1: Enable WDT

The WDTE bit is not used if ENWDT, the Code Option bit ENWD is "0".

That is, if the ENWDT bit is "0", WDT is always disabled no matter what the

WDTE bit is.

The WDTE bit can be read and written to.

Bit 4 (SLPC) This bit is set by hardware at a falling edge of the wake-up signal and is

cleared by software. The SLPC is used to control the oscillator operation.

The oscillator is disabled (oscillator stops, and the controller enters the

Sleep 2 mode) on the high-to-low transition and is enabled (the controller

is awakened from Sleep 2 mode) on a low-to-high transition.

EM78452WM Datasheet(PDF) 16 Page - ELAN Microelectronics Corp

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