MAS9090B datasheet(16/30 Pages) MICRONAS

16 / 30 page

DA9090B.001

January 14, 1998

FUNCTIONAL DESCRIPTION

x Operating Modes

When power is first applied, power-on reset circuit

initializes control and data registers of MAS9090

and puts it into a power-down state. During power-

down state, control registers retain their initial state

until they are written via the serial interface. Master

clock (MCLK) can be inactive.

The power up/down control is accomplished by

changing the P-bit of the address byte of the serial

interface ("0" means active and "1" power-down) or

by stopping the master clock.

power-

down

power-

power-on

reset

P=0, active MCLK and FS

P=1

no MCLK

x Control Interface

Control information or data is written into or read-

back from the internal registers of MAS9090 via the

serial control port. Serial control port consists of

control output CO, control input CI, chip select CS-

and

control

clock

CCLK

and

supports

the

MICROWIRE

™*) communication protocol. All

control instructions, except the single byte power

up/down command require two bytes of data.

To shift the data into MAS9090, CCLK must be

pulsed eight times (CS is low). Data on the CI input

is shifted into the serial input register on the rising

edges of CCLK pulses. After 8 bit address data is

shifted in, the content of the shift register is decoded

and may indicate that 8 bit control word will follow.

Control word may start immediately after the

address byte or after a single CS pulse. It is not

mandatory for the CS signal to return high in

between the address and the data. After the second

byte is shifted in, the CS signal must return to a high

state.

The same process takes place for reading-back

status information during the next CS low state. CS

will remain low for eight CCLK pulses. The data is

shifted out on the CO output from the serial output

high, the CO pin is in a high impedance state, which

enables CO pins of other devices to be multiplexed

together.

x Digital Data Interface

Digital data is shifted in/out from RX/TX using

master clock (MCLK) and Frame Sync (FS) signals.

FS determines the beginning of frame and its

duration can vary from single cycle of MCLK to

squarewave.

Three different modes between FS and the first time

slot of a data frame can be used: non-delayed

normal data timing, non-delayed reverse data timing

and delayed data timing. These modes are set with

bits DM0 and DM1 of control register CR1.

In non-delayed timing modes the first time slot

begins coincident with the rising edge of the FS. In

delayed timing mode the FS must be active at least

one half cycle of MCLK before the beginning of the

first time slot.

Bit EN of control register CR1 enables the voice

data transfer on TX and RX pins. Data is shifted out

from TX output on the rising edge of MCLK and

shifted into RX on falling edge of MCLK on assigned

time slot. In non-delayed reverse mode the data is

shifted with different edge of MCLK (on falling edge

from TX and on rising edge into RX). TX output is in

tristate condition during non selected time slots. The

TX output transmits 8 bits of encoded data (A-law or

µ-law) or 16 bits (14 effective bits, 2 LSB bits zero)

of linear data when compressor is bypassed.

Two time slots (B1 and B2) can be used in two

formats: in Format 1, time slot B1 corresponds to

eight MCLK cycles starting immediately after the

rising

edge

and

time

slot

starts

immediately after the B1 is ended. A two-bit space

is left after B2 for insertion of possible D channel

data. The position of this two-bit data is changed in

Format 2 to the center of time slots B1 and B2. The

data format is selected by bit FF in control register

CR0 and time slots B1 and B2 are selected by bit

TS in control register CR1.

x Control Channel Access to PCM Interface

When companded code is selected it is possible to

access the selected time slot (B1 or B2) by writing

data bytes to internal registers CR2 and CR3. The

byte written to CR3 is transmitted from TX with the

following frame in place of PCM data if bit MX (3) of

CR1 is selected. To implement a continuous data

flow from interface to B channel a control byte has

to be sent on each PCM frame.

The byte written into CR2 is sent through the

receive audio path (RX) if bit MR (4) of CR1 is

selected. CR2 can also be used to read the RX

input. In order to implement a continuous data flow

from B channel to the interface, register CR2 has to

be read at each PCM frame.

*) Trade Mark of National Semiconductor

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