ACT88430 datasheet(50/74 Pages) QORVO

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Data Sheet Rev. G, August 2021 | Subject to change without notice

50 of 74

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ACT88430

Advanced PMU for Microcontrollers and Solid State Drive Applications

nRESET

nRESET is triggered from LDO3. It goes high 1ms after LDO3 goes into regulation.

nRESET_AUX1

The nRESET_AUX1 pin is not functional with CMI 102. Leave the nRESET_AUX1 pin floating.

nRESET_AUX2

The nRESET_AUX2 pin is not functional with CMI 102. Leave the nRESET_AUX2 pin floating.

EXT_PG

EXT_PG is the DVS control input for Buck4. When EXT_PG = L, Buck4 = 1.8V. When EXT_PG = H, Buck4 = 1.2V

MODE

The MODE pin must be tied to ground.

GPIO

The GPIO pin is the input trigger for Buck1. When GPIO goes high, Buck1 turns on and starts the turn on sequencing.

When GPIO goes low, all outputs immediately turn off.

Buck1/2/3 Voltage Setting

Buck1/2/3 reference voltage is 0.6V. This sets the allowable voltage range between 0.6V to 3.000V in 9.375mV steps.

LDO1/3 Voltage Setting

The LDO1/3 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.

LDO2 Voltage Setting

The LDO2 reference voltage is 0.6V. This sets the allowable voltage range between 0.8V to 2.375V in 25mV steps.

Device ID

The CMI 102 Device ID (register 0x7Dh) = 0x00h

I2C Address

The CMI 102 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

ACT88430 Datasheet(PDF) 50 Page - Qorvo, Inc