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Data Sheet

AD5602/AD5612/AD5622

SERIAL INTERFACE

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Rev. F | 17 of 24

POWER-ON RESET

The AD5602/AD5612/AD5622 each contain a power-on reset circuit

that controls the output voltage during power-up. The DAC register

is filled with zeros and the output voltage is 0 V where it remains

until a valid write sequence is made to the DAC. This is useful in

applications in which it is important to know the state of the DAC

output while it is in the process of powering up.

POWER-DOWN MODES

The AD5602/AD5612/AD5622 each contain four separate modes of

operation. These modes are software programmable by setting Bit

PD1 and Bit PD0 in the control register. Table 8 shows how the

state of the bits corresponds to the mode of operation of the device.

Table 8. Modes of Operation

PD1

PD0

Operating Mode

Normal operation

Power-down (1 kΩ load to GND)

Power-down (100 kΩ load to GND)

Power-down (Three-state output)

When both bits are set to 0, the device works normally with its usual

power consumption of 100 µA maximum at 5 V. However, for the

three power-down modes, the supply current falls to <150 nA (at

3 V). Not only does the supply current fall, but the output stage

is internally switched from the output of the amplifier to a resistor

network of known values. This gives the advantage of knowing the

output impedance of the device while the device is in power-down

mode. There are three different options. The output is connected

internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or it is

left open circuited (three-state). Figure 42 shows the output stage.

Figure 42. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other as-

sociated linear circuitry are all shut down when the power-down

mode is activated. However, the contents of the DAC register are

unaffected when in power-down. The time to exit power-down is

typically 14 µs for VDD = 5 V and 17 µs for VDD = 3 V (see Figure

29).

WRITE OPERATION

When writing to the AD5602/AD5612/AD5622, the user must begin

with a start command followed by an address byte (R/W) = 0), after

which the DAC acknowledges that it is prepared to receive data by

pulling SDA low.

Two bytes of data are then written to the DAC, the most significant

byte followed by the least significant byte as shown in Figure

43; both of these data bytes are acknowledged by the AD5602/

AD5612/AD5622. A stop condition follows. The write operations for

the three DACs are shown in Figure 43, Figure 44, and Figure 45.

Figure 43. AD5602 Write Sequence

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