AX88772ALF datasheet(16/45 Pages) ASIX

16 / 45 page

ASIX ELECTRONICS CORPORATION

AX88772A/AX88172A

Low-pin-count

USB 2.0 to 10/100M Fast Ethernet Controller

GND18A

9, 64

Analog Ground for Ethernet PHY and 25Mhz crystal oscillator.

2.2 AX88172A 80-pin Pinout Description

Table 2

: AX88172A 80-pin Pinout Description

Pin Name

Type

Pin No

Pin Description

USB Interface

USB 2.0 data positive pin.

USB 2.0 data negative pin.

VBUS

I5/PD/S

VBUS pin input. Please connect to USB bus power.

XTL12P

12Mhz ±0.003%crystal or oscillator clock input. This clock is needed for

USB PHY transceiver to operate.

XTL12N

12Mhz crystal or oscillator clock output.

RREF

For USB PHY’s internal biasing. Please connect to analog GND through a

resistor (12.1Kohm ±1%).

Serial EEPROM Interface

EECK

B5/PD/

EEPROM Clock. EECK is an output clock to EEPROM to provide timing

reference for the transfer of EECS, and EEDIO signals. EECK only drive

high / low when access EEPROM otherwise keep at tri-state and internal

pull-down.

EECS

B5/PD/

EEPROM Chip Select. EECS is asserted high synchronously with respect

to rising edge of EECK as chip select signal. EECS only drive high / low

when access EEPROM otherwise keep at tri-state and internal pull-down.

EEDIO

B5/PU/

EEPROM Data In. EEDIO is the serial output data to EEPROM’s data

input pin and is synchronous with respect to the rising edge of EECK.

EEDIO only drive high / low when access EEPROM otherwise keep at

tri-state and internal pull-up.

Ethernet PHY Interface

XTL25P

I18

25Mhz ± 0.005% crystal or oscillator clock input. This clock is needed for

the embedded 10/100M Ethernet PHY to operate.

XTL25N

O18

25Mhz crystal or oscillator clock output.

RXIP

Receive data input positive pin for both 10BASE-T and 100BASE-TX.

RXIN

Receive data input negative pin for both 10BASE-T and 100BASE-TX.

TXOP

Transmit data output positive pin for both 10BASE-T and 100 BASE-TX

TXON

Transmit data output negative pin for both 10BASE-T and 100 BASE-TX

RSET_BG

For Ethernet PHY’s internal biasing. Please connect to GND through a

12.1Kohm ±1% resistor.

LINK_LED

Link status LED indicator. This pin drives low continuously when the

Ethernet link is up and drives low and high in turn (blinking) when

Ethernet PHY is in receiving or transmitting state.

FDX_LED

Full Duplex and collision detected LED indicator. This pin drives low

when the Ethernet PHY is in full-duplex mode and drives high when in

half duplex mode. When in half duplex mode and the Ethernet PHY

detects collision, it will be driven low (or blinking).

SPEED_LED

Ethernet speed LED indicator. This pin drives low when the Ethernet PHY

is in 100BASE-TX mode and drives high when in 10BASE-T mode.

Misc. Pins

RESET_N

I5/PU/S

Chip Reset Input. RESET_N pin is active low. When asserted, it puts the

entire chip into reset state immediately. After completing reset, EEPROM

data will be loaded automatically.

EXTWAKEUP_N I5/PU/S

Remote-wakeup trigger from external pin. EXTWAKEUP_N should be

asserted low for more than 2 cycles of 12MHz clock to be effective.

GPIO_2 / RXER B5/PD

General Purpose Input/ Output Pin 2. This pin is GPIO_2 in MAC mode,

but it will be redefined as RXER (receive error) or GPIO_2 depending on

EEPROM Flag [3]

in PHY mode.

AX88772ALF Datasheet(PDF) 16 Page - ASIX Electronics Corporation

AX88772ALF Datasheet(HTML) 16 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL