AX88772ALF datasheet(19/45 Pages) ASIX

19 / 45 page

ASIX ELECTRONICS CORPORATION

AX88772A/AX88172A

Low-pin-count

USB 2.0 to 10/100M Fast Ethernet Controller

TXEN

I5/PD

Transmit Enable from the externally connected Ethernet MAC device with

RMII.

TXD [1:0]

I5/PD

22, 23 Transmit Data from the externally connected Ethernet MAC device with

RMII.

I5/PD

19, 20 NC

O3/PD

31, 32 NC

RXER

O3/PD/T

Receive Error. RXER is always driven low by AX88172A in

Reverse-RMII mode. This pin is tri-stated in isolate mode.

MIS_1

I5/PD

External Media Interface Select 1. This is used as Chip Operation Mode

selection pin; please refer to section 2.3 Settings.

MIS_0

I5/PD

External Media Interface Select 0. This is used as Chip Operation Mode

selection pin; please refer to section 2.3 Settings.

REFCLK_O

50Mhz Reference clock output. If the externally connected Ethernet MAC

device can’t supply 50Mhz reference clock, this clock can be used to

supply to the REF_CLK of externally connected Ethernet MAC device

with RMII and the REFCLK_I of this chip.

CRSDV

O3/T

Carrier Sense and Receive Data Valid to the externally connected Ethernet

MAC device with RMII. This pin is tri-stated in isolate mode.

RXD [1:0]

O3/T

61, 62 Receive Data to the externally connected Ethernet MAC device with

RMII. These pins are tri-stated in isolate mode.

MDC

I5/PD

Station Management clock input from the externally connected Ethernet

MAC device. All data transferred on MDIO are synchronized to the rising

edge of this clock.

MDIO

B5/PU

Station Management Data. Serial data input/output transferred from/to the

externally connected MAC device. The transfer protocol should conform

to the IEEE 802.3u MII spec.

AX88772ALF Datasheet(PDF) 19 Page - ASIX Electronics Corporation

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