AX88772ALF datasheet(17/45 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88772A/AX88172A

Low-pin-count

USB 2.0 to 10/100M Fast Ethernet Controller

GPIO_1

B5/PD

General Purpose Input/ Output Pin 1. This pin is default as input pin after

power-on reset. This pin is also for Default WOL Ready Mode setting;

please refer to section 2.3 Settings.

GPIO_0 / PME

B5/PD

General Purpose Input/ Output Pin 0 or PME (Power Management Event).

This pin is default as input pin after power-on reset. GPIO_0 also can be

defined as PME output to indicate wake up event detected. Please refer to

section 2.3 Settings.

SI_3

B5/PU

UART_RX or SPI_MISO. This is a multi-function pin determined by

EEPROM Flag [1] setting. Please refer to section 2.3 Settings.

SI_2

B5/PU

UART_TX or SPI_MOSI. This is a multi-function pin determined by

EEPROM Flag [1] setting. Please refer to section 2.3 Settings.

SI_1

B5/PU

I2C_SDA or SPI_SS. This is a multi-function pin determined by

EEPROM Flag [1] setting. Please refer to section 2.3 Settings.

SI_0

B5/PU

I2C_SCLK or SPI_SCLK. This is a multi-function pin determined by

EEPROM Flag [1] setting. Please refer to section 2.3 Settings.

USB_LED

USB Speed indicator: When USB bus is in Full speed, this pin drives high

continuously. When USB bus is in High speed, this pin drives low

continuously. This pin drives high and low in turn (blinking) to indicate

TX data transfer going on whenever the host controller sends bulk out data

transfer.

TEST0

I5/S

Test pin. For normal operation, user should connect to ground.

TEST1

I5/S

Test pin. For normal operation, user should connect to ground.

TCLK_EN

I5/PD/S

Test pin. For normal operation, user should keep this pin NC.

TCLK_0

I5/PD

Test pin. For normal operation, user should keep this pin NC.

TCLK_1

I5/PD

Test pin. For normal operation, user should keep this pin NC.

On-chip Regulator Pins

VCC3R3

3.3V Power supply to on-chip 3.3V-to-1.8V voltage regulator.

GND3R3

Ground pin of on-chip 3.3V-to-1.8V voltage regulator.

V18F

1.8V voltage output of on-chip 3.3V-to-1.8V voltage regulator.

Power and Ground Pins

VCCK

13, 14, 27, 33,

41, 57, 66,

Digital Core Power. 1.8V.

VCC3IO

21, 51, 65

Digital I/O Power. 3.3V.

GND

15, 16, 29, 42,

55, 56, 76

Digital Ground.

VCC33A_H

Analog Power for USB transceiver. 3.3V.

GND33A_H

Analog Ground for USB transceiver.

VCC33A_PLL

Analog Power for USB PLL. 3.3V.

GND33A_PLL

Analog Ground for USB PLL.

VCC3A3

Analog Power for Ethernet PHY bandgap. 3.3V.

GND3A3

Analog Ground for Ethernet PHY.

VCC18A

6, 77

Analog Power for Ethernet PHY and 25Mhz crystal oscillator. 1.8V.

GND18A

9, 80

Analog Ground for Ethernet PHY and 25Mhz crystal oscillator.

External Media Interface: MAC Mode with MII Interface

RXCLK

I5/PD

Receive Clock. RXCLK is received from PHY to provide timing reference

for the transfer of RXD [3:0] and RXDV signals on receive direction of

MII interface.

RXDV

I5/PD

Receive Data Valid. RXDV is asserted high when valid data is present on

RXD [3:0]. It is driven synchronously with respect to RXCLK by PHY.

RXD [3:0]

I5/PD

19, 20,

22, 23

Receive Data. RXD [3:0] is driven synchronously with respect to RXCLK

by PHY.

CRS

I5/PD

Carrier Sense. CRS is asserted high asynchronously by the PHY when

either transmit or receive medium is non-idle.

COL

I5/PD

Collision. COL is driven high by PHY when the collision is detected.

AX88772ALF Datasheet(PDF) 17 Page - ASIX Electronics Corporation

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