AX88772ALF datasheet(18/45 Pages) ASIX

18 / 45 page

ASIX ELECTRONICS CORPORATION

AX88772A/AX88172A

Low-pin-count

USB 2.0 to 10/100M Fast Ethernet Controller

TXCLK

I5/PD

Transmit Clock. TXCLK is received from PHY to provide timing

reference for the transfer of TXD [3:0] and TXEN signals on transmit

direction of MII interface.

TXEN

Transmit Enable. TXEN is asserted high to indicate a valid TXD [3:0]. It is

transitioned synchronously with respect to the rising edge of TXCLK.

TXD [3:0]

59, 60,

61, 62

Transmit Data. TXD [3:0] is transitioned synchronously with respect to

the rising edge of TXCLK. Note TXD [3:2] are also used as Chip

Operation Mode selection pins; please refer to section 2.3 Settings.

MDC

O3/PD

Station management clock output to PHY. All data transferred on MDIO

are synchronized to the rising edge of this clock. The frequency of MDC is

1.5MHz.

MDIO

B5/PU

Station management data input/output. Serial data input/output transferred

from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII

spec.

External Media Interface: PHY Mode with Reverse-MII Interface

TXCLK

O3/T

Transmit Clock. This clock is provided to supply to the TX_CLK of

externally connected Ethernet MAC device with MII. This pin is tri-stated

in isolate mode.

TXEN

I5/PD

Transmit enable. TXEN is asserted high to indicate a valid TXD [3:0]. It

should be driven synchronously with respect to the rising edge of TXCLK

by the externally connected Ethernet MAC device with MII.

TXD [3:0]

I5/PD

19, 20,

22, 23

Transmit Data. TXD [3:0] should be driven synchronously with respect to

the rising edge of TXCLK by the externally connected Ethernet MAC

device with MII.

CRS

O3/PD/T

Carrier Sense. CRS is asserted high by AX88172A when RXDV is

asserted high in Reverse-MII mode. This pin is tri-stated in isolate mode.

COL

O3/PD/T

Collision. COL is always driven low because AX88172A is operating in

100M/full-duplex mode internally in Reverse-MII mode. This pin is

tri-stated in isolate mode.

RXER

O3/PD/T

Receive Error. RXER is always driven low by AX88172A in Reverse-MII

mode. This pin is tri-stated in isolate mode.

RXCLK

O3/T

Receive clock. This clock is provided to supply to the RX_CLK of

externally connected Ethernet MAC device with MII. This pin is tri-stated

in isolate mode.

RXDV

O3/T

Receive Data Valid. RXDV is asserted high when valid data is present on

RXD [3:0]. It is transitioned synchronously with respect to RXCLK from

AX88172A to the externally connected Ethernet MAC device with MII.

This pin is tri-stated in isolate mode.

RXD [3:0]

O3/T

59, 60,

61, 62

Receive Data. RXD [3:0] is transitioned synchronously with respect to

RXCLK from AX88172A to the externally connected Ethernet MAC

device with MII. Note that RXD [3:2] are also used as Chip Operation

Mode selection pins. Please refer to section 2.3 Settings. These pins are

tri-stated in isolate mode.

MDC

I5/PD

Station Management clock input from the externally connected Ethernet

MAC device. All data transferred on MDIO are synchronized to the rising

edge of this clock.

MDIO

B5/PU

Station Management Data. Serial data input/output transferred from/to the

externally connected MAC device. The transfer protocol should conform

to the IEEE 802.3u MII spec.

External Media Interface: PHY Mode with Reverse-RMII Interface

REFCLK_I

50Mhz +/-50ppm Reference clock input for RMII receive, transmit and

control signals. If externally connected Ethernet MAC device with RMII

can’t provide 50Mhz Reference clock to AX88172A, then user can

connect this pin to REFCLK_O and use REFCLK_O to supply clock to

the externally connected Ethernet MAC device at the same time.

AX88772ALF Datasheet(PDF) 18 Page - ASIX Electronics Corporation

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