500

1000

1500

2000

2500

3000

0

10

20

30

40

50

RISE TIME (ps)

CLC007

SNLS016E – JULY 1998 – REVISED APRIL 2013

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Output Rise And Fall Times

Output load capacitance can significantly affect output rise and fall times. The effect of load capacitance, stray or

otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing

all interconnecting trace lengths. Figure 10 shows the effect on risetime of parallel load capacitance across a

150

Ω load.

Figure 10. Rise Time vs CL

PCB Layout Recommendations

Printed circuit board layout affects the performance of the CLC007. The following guidelines will aid in achieving

satisfactory device performance.

•

Use a ground plane or power/ground plane sandwich design for optimum performance.

•

Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum

electrolytic capacitor located no more than 0.1” (2.5 mm) from the device power pins.

•

Provide short, symmetrical ground return paths for:

–

Inputs,

–

Supply bypass capacitors and

–

The output load.

•

Provide short, grounded guard traces located

–

Under the centerline of the package,

–

0.1” (2.5 mm) from the package pins

–

On both top and bottom of the board with connecting vias.

8

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