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DAC1280IPWR Datasheet(PDF) 5 Page - Texas Instruments |
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DAC1280IPWR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 26 page ![]() 1 2 3 4 5 6 7 8 CLK TDATA t CTHD t TSOP t TCSU t SCSU t CPW t CPW t CLK DAC OUTPUT 21 TDATA Sample 9 Next TDATA Sample t SYLW t STDAT t TDATA SYNC Output Hold Output Update DAC1280 www.ti.com SBAS432A – APRIL 2010 – REVISED SEPTEMBER 2010 TIMING CHARACTERISTICS space Figure 1. TIMING REQUIREMENTS At TA = –40°C to +85°C and DVDD = 1.65V to 3.6V. PARAMETER MIN TYP MAX UNIT tCLK CLK period (1/fCLK) 240 1000 ns tCPW CLK high or low pulse width 100 ns tSCSU SYNC rising edge to CLK rising edge setup time 30 ns tTCSU TDATA to CLK rising edge setup time 30 ns tCTHD CLK rising edge to TDATA hold time 10 ns tSYLW SYNC low pulse width 2 tCLK tSTDAT Rising CLK after SYNC high to TDATA sample time 5 tCLK tTSOP TDATA sample to output update 4 tCLK tTDATA TDATA period 16 tCLK Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): DAC1280 |
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