SDA

SCL

S

P

START condition

STO

P condition

LM48560

SNAS513F – AUGUST 2011 – REVISED NOVEMBER 2015

www.ti.com

Electrical Characteristics VDD = 3.6 V (continued)

The following specifications apply for RL = 1.5 μF + 10 Ω, CBST = 1 μF, CIN = 0.47 μF, CSET = 100 nF, AV = 24 dB unless

otherwise specified. Limits apply for TA = 25 °C.

(1)(2)

PARAMETER

TEST CONDITIONS

MIN (3)

TYP (4)

MAX (3)

UNIT

TA

Attack time

ATK1:ATK0 = 00, CSET = 100 nF

0.83

ms

TR

Release time

RLT1:RLT0 = 00, CSET = 100 nF

0.5

s

Boost converter switching

fSW

2

MHz

frequency

ILIMIT

Boost converter current limit

1.5

A

VIH

Logic high input threshold

SHDN

1.4

V

VIL

Logic low input threshold

SHDN

0.5

V

IIN

Input leakage current

SHDN

0.1

0.2

μA

6.5 I

2C Interface Characteristics

The following specifications apply for RPU = 1 kΩ to VDD, SW/HW = 1 (Software Mode) unless otherwise specified. Limits

apply for TA = 25 °C.

(1) (2)

PARAMETER

TEST CONDITIONS

MIN (3)

TYP (4)

MAX (3)

UNIT

VIH

Logic Input High Threshold

SDA, SCL

1.1

V

VIL

Logic Input Low Threshold

SDA, SCL

0.5

V

SCL Frequency

400

kHz

t1

SCL Period

2.5

μs

t2

SDA Setup Time

250

ns

t3

SDA Stable Time

250

ns

t4

Start Condition Time

250

ns

t5

Stop Condition Time

250

ns

(1)

All voltages are measured with respect to the ground pin, unless otherwise specified.

(2)

The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(3)

Typical values represent most likely parametric norms at TA = 25 ºC, and at the Recommended Operation Conditions at the time of

product characterization and are not ensured.

(4)

Charge device model, applicable std. JESD22-C101-C.

Figure 1. I2C Timing Diagram

Figure 2. Start and Stop Diagram

6

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