LMK02002

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SNAS418 – AUGUST 2007

REGISTER R4 to R7

Registers R4 through R7 control the eight clock outputs. Register R4 controls CLKout0, Register R5 controls

CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of

these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the

actual clock output which may be from 0 to 3.

RESET bit -- R0 only

This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit

to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. If this bit is

set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and

RESET = 0.

Default

Bit

Bit Name

Bit State

Bit Description

Register

Bit Value

Location

RESET

0

No reset, normal operation

Reset to power on defaults

R0

31

CLKoutX_MUX

0

Bypassed

CLKoutX mux mode

18:17

CLKoutX_EN

0

Disabled

CLKoutX enable

16

R4 to R7

CLKoutX_DIV

1

Divide by 2

CLKoutX clock divide

15:8

CLKoutX_DLY

0

0 ps

CLKoutX clock delay

7:4

DIV4

0

PDF

≤ 20 MHz

Phase Detector Frequency

R11

15

EN_CLKout_Global

1

Normal - CLKouts normal

Global clock output enable

27

POWERDOWN

0

Normal - Device active

Device power down

26

PLL_CP_TRI

0

Normal - PLL active

TRI-STATE PLL charge pump

25

R14

PLL_CP_POL

0

Negative Polarity CP

Polarity of charge pump

24

PLL_MUX

0

Disabled

Multiplexer control for LD pin

23:20

PLL_R

10

R divider = 10

PLL R divide value

19:8

PLL_CP_GAIN

0

100 uA

Charge pump current

31:30

R15

PLL_N

760

N divider = 760

PLL N divide value

25:8

CLKoutX_MUX[1:0] -- Clock Output Multiplexers

These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes

changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode. The different

MUX modes and associated delays are listed below.

CLKoutX_MUX[1:0]

Mode

Added Delay Relative to Bypass Mode

0

Bypassed (default)

0 ps

1

Divided

100 ps

400 ps

2

Delayed

(In addition to the programmed delay)

500 ps

3

Divided and Delayed

(In addition to the programmed delay)

CLKoutX_DIV[7:0] -- Clock Output Dividers

These bits control the clock output divider value. In order for these dividers to be active, the respective

CLKoutX_MUX (See CLKoutX_MUX[1:0] -- Clock Output Multiplexers) bit must be set to either "Divided" or

"Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all

edges of the clock outputs are aligned (See GLOBAL CLOCK OUTPUT SYNCHRONIZATION). The Clock

Output Dividers follow the VCO Divider so the final clock divide for an output is VCO Divider × Clock Output

Divider. By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred.

The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.

Copyright © 2007, Texas Instruments Incorporated

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