LMK02002

SNAS418 – AUGUST 2007

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CLKoutX_DIV[7:0]

Clock Output Divider value

0

0

0

0

0

0

0

0

Invalid

0

0

0

0

0

0

0

1

2 (default)

0

0

0

0

0

0

1

0

4

0

0

0

0

0

0

1

1

6

0

0

0

0

0

1

0

0

8

0

0

0

0

0

1

0

1

10

.

.

.

.

.

.

.

.

...

1

1

1

1

1

1

1

1

510

CLKoutX_DLY[3:0] -- Clock Output Delays

These bits control the delay stages for each clock output. In order for these delays to be active, the respective

CLKoutX_MUX (See CLKoutX_MUX[1:0] -- Clock Output Multiplexers) bit must be set to either "Delayed" or

"Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps

is incurred in addition to the delay shown in the table below.

CLKoutX_DLY[3:0]

Delay (ps)

0

0 (default)

1

150

2

300

3

450

4

600

5

750

6

900

7

1050

8

1200

9

1350

10

1500

11

1650

12

1800

13

1950

14

2100

15

2250

CLKoutX_EN bit -- Clock Output Enables

These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See

EN_CLKout_Global bit -- Global Clock Output Enable) is set to zero or if GOE pin is held low, all CLKoutX_EN

bit states will be ignored and all clock outputs will be disabled. See CLKout OUTPUT STATES for more

information on CLKout states.

CLKoutX_EN bit

Conditions

CLKoutX State

0

EN_CLKout_Global bit = 1

Disabled (default)

GOE pin = High / No Connect 1

1

Enabled

REGISTER R11

This register only has one bit and only needs to be programmed in the case that the phase detector frequency is

greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to the correct values.

DIV4

This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable

output from the digital lock detect output in the case of a phase detector frequency greater than 20 MHz.

12

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